Engineer F/M Dynamic Approximate Computing for Energy-Efficient AI Hardware Accelerators

Inria; Rennes; Hybrid; EUR 27,000 - 33,000; Full time

Benefits offered by this job

Teleworking after 6 months

7 weeks annual leave + RTT

Professional equipment

Social, cultural and sports events

Job summary

Inria Rennes Center invites applications for an Engineer F/M to develop energy-efficient AI hardware accelerators using dynamic approximate computing. The role blends hardware design, computer architecture, and co-design with software to push performance and efficiency for edge and data-center AI workloads.

You will model, simulate, and prototype techniques like pruning and mixed-precision arithmetic, and present findings to a research team.

Qualifications

• Master’s degree in Computer Engineering or related fields.
• Strong HW design skills with VHDL/Verilog knowledge.
• Experience with ML frameworks (PyTorch/TensorFlow).
• Knowledge of approximate computing techniques (e.g., pruning, mixed precision).
• Excellent analytical and problem‑solving abilities; focus on energy efficiency.
• Strong communication skills and ability to present research clearly.
• English proficiency (written and spoken).
• Ability to work in a research team and present progress regularly.

Responsibilities

• Investigate and advance energy-efficient AI accelerators using dynamic approximate computing.
• Develop hardware-software co-design methodologies.
• Model, simulate, and prototype with representative AI workloads.
• Systematically evaluate robustness and scalability of proposed approaches.

Skills

HW design

Computer architecture

ML frameworks

Approximate computing

Analytical skills

Communication

English proficiency

Teamwork

Education

Master's degree in Computer Engineering

Job description

Engineer F/M Dynamic Approximate Computing for Energy-Efficient AI Hardware Accelerators

The Inria center at the University of Rennes is one of eight Inria centers and has more than thirty research teams. The Inria center is a major and recognized player in the field of digital sciences. It is at the heart of a rich ecosystem of R&D and innovation, including highly innovative SMEs, large industrial groups, competitiveness clusters, research and higher education institutions, centers of excellence, and technological research institutes.

Context and Background

As artificial intelligence expands across edge devices, data centers, and embedded systems, the demand for computational power has grown dramatically. Deep neural networks require billions of arithmetic operations and move vast amounts of data, which drives up both energy consumption and hardware complexity. Specialized accelerators like GPUs and TPUs have delivered significant improvements over general-purpose processors, yet the increasing scale of AI models continues to push power and thermal limits. This becomes particularly challenging for edge and battery-powered devices, where energy efficiency determines not just performance but practical viability and long-term sustainability.

Approximate computing offers a compelling approach to these energy constraints by trading some computational precision for improvements in power efficiency, performance, and chip area. The fundamental insight is that many AI applications, such as image recognition, speech processing, and recommendation systems, can tolerate a degree of error. Neural networks are particularly resilient, maintaining acceptable accuracy even when operations use reduced precision, simplified circuits, or probabilistic components. Leveraging this tolerance allows designers to reduce switching activity, memory bandwidth, and overall hardware complexity.

For AI hardware accelerators, approximate computing can be implemented across multiple design layers: algorithmic techniques like model pruning and quantization, architectural approaches such as approximate memory hierarchies, and circuit-level methods including approximate multipliers and adders. Together, these strategies can substantially reduce both dynamic and static power while keeping application performance within acceptable error margins. As AI deployment scales from resource-constrained edge devices to large data centers, approximate computing has become an essential research direction for achieving sustainable and energy-efficient acceleration.

The primary objective of thisjob is to investigate and advance thedesign of energy-efficient AI accelerators by dynamically applyingapproximate computingtechniques and to advancehardware-software co-design methodologies.

The research will build upon recent advancements in efficient domain-specific architectures for AI. The goal is to develop novel approaches that balance performance, energy efficiency, and accuracy, while addressing the unique challenges of implementing approximate computing in real-world AI systems.

This research explores the principles and practical implications of approximate computing as a pathway toward more energy-efficient AI hardware accelerators. It examines how different forms of approximation affect computational efficiency, prediction accuracy, and overall system-level performance. Rather than treating these techniques in isolation, the study considers their combined impact across the computing stack, with particular attention to how accuracy-efficiency trade-offs can be characterized and controlled.

A central theme of the work is the integration of hardware and software perspectives through a co-design approach. By closely aligning algorithmic characteristics with architectural features, the research aims to uncover strategies for embedding approximation mechanisms directly into accelerator designs. Emphasis is placed on adaptive and context-aware approximation techniques that can dynamically balance energy savings and output quality, ensuring that efficiency gains do not compromise application-level requirements.

To ground these ideas in practice, the research involves modeling, simulation, and experimental prototyping using representative AI workloads, including deep learning inference and computer vision applications. Through systematic evaluation and validation, the study aims to assess the feasibility, robustness, and scalability of proposed approaches, contributing insights into the design of next-generation energy-efficient AI systems.

Required Skills

We seek highly motivated and passionate candidates. Autonomy is a highly appreciated quality.

Candidates should possess the following qualifications:

• Strong HW design skills: VHDL/Verilog, HW synthesis flow (design, simulation, synthesis, and deployment through commercial tools for FPGA or ASIC)
• Strong foundation in computer architectureand Systems design. Knowledge about hardware architectures of Neural Network accelerators is a plus.
• Familiarity or Experience with machine learning fundamentals and Deep Neural Network development frameworks, e.g., PyTorch/TensorFlow
• Experience with approximate computing techniques (e.g., functional approximation, mixed-precision arithmetic, pruning) is a significant plus.
• Excellent analytical and problem-solving abilities, with an interest in optimizing for energy efficiency.
• Strong communication skills to articulate research findings clearly and effectively.
• Languages: proficiency in written English and fluency in spoken English are required.
• Relational skills:thecandidatewillworkin a research team, where regular meetings will be set up.The candidatehas to be able to present the progress oftheir work in a clear and detailed manner.
• Othervalues appreciated areopen-mindedness, strong integration skills,and team spirit.

Candidates must have a Master’s degree (or equivalent) inComputer Engineeringorrelated areas relevant to the PhD topic.

Talented last year Master’s students may start as 6-month interns and continue as Ph.D. researchers after graduation.

Avantages

• Partial reimbursement of public transport costs
• Leave: 7 weeks of annual leave + 10 extra days off due to RTT (statutory reduction in working hours) + possibility of exceptional leave (sick children, moving home, etc.)
• Possibility of teleworking (after 6 months of employment) and flexible organization of working hours
• Professional equipment available (videoconferencing, loan of computer equipment, etc.)
• Social, cultural and sports events and activities

monthly gross salary 2695 eurosaccording to diploma and experience

Candidates withknowledge and experience in at least one of the following areas arehighlyvalued:Hardware Design, Hardware/Softwareco-design.

We seekhighly motivated and passionatecandidates.Autonomyis a highly appreciated quality.

Candidates must have a Master’s degree (or equivalent) inComputer Engineering orrelated areas relevant to the PhD topic