Avionics FPGA Design & Verification Engineer (Entry)

Airbus; Toulouse; Sur place; EUR 45 000 - 65 000; Plein temps

Résumé du poste

Airbus Operations SAS in Toulouse, France, is seeking an FPGA design and verification engineer to join the Electronics Products Department in the Avionics and Simulation domain. The role focuses on PLD design and verification for embedded avionics hardware across Airbus aircrafts.

You should bring FPGA design and verification flow knowledge (including UVM), VHDL, SystemVerilog, Python, and tools such as Modelsim/Questa, Synplify, and Matlab/Simulink.

Qualifications

• Experience with PLD design and verification for avionics hardware.
• Knowledge of HDL languages including VHDL and SystemVerilog.
• Familiarity with UVM verification methodology.
• Ability to work in a multidisciplinary team.
• Security clearance or eligibility required.

Responsabilités

• Being responsible for PLD subfunction development, within a team, and with a focus on verification topic.
• Contributing to electronics R&D.
• Proposing innovative ideas in the FPGA field for continuous improvement.
• Performing activities on-schedule, on cost and on-quality.

Connaissances

FPGA design

Verification

UVM basics

VHDL

SystemVerilog

Python

C/Assembler

Outils

Modelsim/Questa

Synplify

Matlab/Simulink

Description du poste

Airbus Operations SAS in Toulouse, France, is seeking an FPGA design and verification engineer to join the Electronics Products Department in the Avionics and Simulation domain. The role focuses on PLD design and verification for embedded avionics hardware across Airbus aircrafts.

You should bring FPGA design and verification flow knowledge (including UVM), VHDL, SystemVerilog, Python, and tools such as Modelsim/Questa, Synplify, and Matlab/Simulink.