Analog and/or RF IC Layout designer

ASYGN; Montpellier; Sur place; EUR 40 000 - 60 000; Plein temps

Résumé du poste

A leading ASIC design house in Montpellier is seeking an Analog and/or RF IC Layout designer responsible for layout and verification of CMOS integrated circuits. Candidates should have experience in analog/RF IC development and be proficient in CAD tools like Cadence and Mentor Calibre. Fluency in English and French is required. Competitive compensation is offered.

Qualifications

• B.S. or M.S in Electrical Engineering degree with experience in analog and/or RF IC development.
• Proficient in written and spoken English and French.

Responsabilités

• Prepare the floorplan of the IPs or the top level chip and validate the constraints from the design.
• Make the layout following the constraints.
• Run all the mandatory verifications and perform parasitic extraction.
• Work in close collaboration with the designers.
• Take into account the constraints of the assembly and the chip packaging.

Connaissances

Analog layout fundamentals

RF layout fundamentals

DRC/LVS debugging

CAD tools (Cadence, Mentor Calibre)

Device matching understanding

Programming (optional)

Formation

B.S. or M.S in Electrical Engineering

Outils

Cadence Virtuoso

Mentor Calibre

Description du poste

Overview

Asygn is an ASIC design house of 35 people which provides system solutions for industrial consumer and automotive applications in RF and inertial sensors fields. Products such as analog front-end chips, boards and software are developed for data acquisition and demonstration purposes. Our flagship product AS321X is a Battery-less Sensing Chip included in demonstration tags which enable wireless and low consumption data acquisition by UHF RFID.

Job Description

ASYGN is seeking an Analog and/or RF IC Layout designer who will be responsible for the layout and verification of CMOS integrated circuit IPs. The candidate must have a proven record of layouting complex mixed signal ICs in state-of-the-art CMOS technologies. The successful candidate will be an enthusiastic achiever, objective-driven, and able to work efficiently with both the IC and applications teams.

Responsibilities

• Prepare the floorplan of the IPs or the top level chip and validate the constraints from the design
• Make the layout following the constraints
• Run all the mandatory verifications (versus the Design Rules Manual), DRC/LVS/... and perform parasitic extraction (PEX/xACT, PVS)
• Work in close collaboration with the designers to find the best compromise in term of cost, area and quality
• Take into account the constraints of the assembly and the chip packaging

Profile

Education And Experience Requirements
B.S. or M.S in Electrical Engineering degree with experience in analog and/or RF IC development.

Additional Qualifications

• Strong grasp of analog / RF layout fundamentals and best practices
• Proficient at debugging/fixing DRC/LVS errors
• Solid knowledge of CAD tools like Cadence Virtuoso suite, Mentor Calibre
• Good understanding of device matching problematics, cross coupling capacitor, electro-migration, IR drop, antenna effect, DFM, latch-up
• Unix OS familiarity strongly desired
• Programming language (skill or other) is as plus but not required
• Eager for field returns and continuous improvement
• Proficient in written and spoken English and French