SoC Verification Engineer — AI-Driven Testing, Flexible Hours

Partech; Tampere; On-site; EUR 42,000 - 54,000; Full time

Benefits offered by this job

Competitive salary

Bonus plan

Insurance plan

Annual vacation

Flexible hours

Family policies

Sports club

Job summary

Partech in Tampere, Finland, is expanding its R&D team to recruit a junior SoC Verification Engineer focused on RTL design, IP integration and verification for Nordic Semiconductor's next-gen chips. The role emphasizes AI-driven verification techniques and cross-disciplinary collaboration.

You will work on test benches, coverage, and debugging in a team creating ultra-low power devices, with opportunities to grow in a cutting-edge environment and learn continuously.

Qualifications

• MSc in electrical engineering or equivalent, or Bachelor with industrial experience.
• Strong knowledge of coverage-based verification, assertion-based, and formal verification techniques.
• Solid working knowledge of HDLs such as Verilog, SystemVerilog and/or VHDL, including SystemVerilog Assertions (SVA).
• Good debugging skills.
• Programming background in low-level and script-based languages, e.g. C, C++, Python, Perl is a plus.
• Interest in, or experience with, using AI tools (e.g. LLM-based coding assistants) in the verification workflow.
• Fluent English language skills (written and oral).

Responsibilities

• SoC/IP subsystem verification planning, test infrastructure development, functional verification.
• Embedded C code or writing CPU-centric tests using C code.
• Coverage definition, implementation and analysis.
• Test bench and test case generation using Verilog, SystemVerilog & UVM.
• Reading, understanding and debugging RTL written in HDLs (Verilog, SystemVerilog) and root-cause analysis.
• Applying AI based tools and techniques to improve verification productivity, e.g. AI-assisted test and testbench generation, intelligent regression management, automated failure triage and accelerated coverage closure.

Skills

HDL verification

SystemVerilog

C/C++

Python

AI tools in verification

English proficiency

Education

MSc in Electrical Engineering or Bachelors with industry experience

Tools

Verilog

SystemVerilog

VHDL

Job description

Partech in Tampere, Finland, is expanding its R&D team to recruit a junior SoC Verification Engineer focused on RTL design, IP integration and verification for Nordic Semiconductor's next-gen chips. The role emphasizes AI-driven verification techniques and cross-disciplinary collaboration.

You will work on test benches, coverage, and debugging in a team creating ultra-low power devices, with opportunities to grow in a cutting-edge environment and learn continuously.