Senior Data Center GPU Systems Engineer (Post-Silicon)

RiseMe; Tampere; On-site; CAD 120,000 - 160,000; Full time

Job summary

AMD is seeking a Sr. Systems Design Engineer for the Data Center GPU team in Markham, ON. You will drive post-silicon validation, debug, and cross-team collaboration to ensure high-quality IP blocks and system performance.

The role emphasizes ownership, scalable solutions, and hands-on debugging across SOC blocks. The position requires expertise in post-silicon validation, with strong C/C++/Python skills and a deep understanding of SoC architectures, DMA, and memory subsystems.

Qualifications

• Experience in post-silicon validation, hardware debug, or a related semiconductor engineering role.
• Programming/scripting skills (e.g., C/C++, Python, Perl).
• Debug techniques and methodologies for post-silicon validation.
• Experience with board/platform-level debugging, including bring-up, sequencing, analysis, and optimization.
• Knowledge of SoC system architecture, including multi-die or chiplet-based designs.
• Understanding of cache hierarchies, buffer allocation and management, ring buffers, FIFO structures, credit-based flow control, and tag tracking mechanisms.
• Familiarity with DMA, interrupt handling, memory subsystem, or I/O subsystem architectures.
• Knowledge of memory management concepts including address translation, virtual memory, TLB operation, and page fault handling.
• Familiarity with software runtime environments, kernel-level drivers, or OS-level interfaces that interact with hardware IPs.
• Exposure to RAS concepts — error detection, poison propagation, machine check logging, and watchdog mechanisms.
• Experience with scan dump analysis or JTAG-based post-silicon debug tools.
• Strong analytical/problem-solving skills and pronounced attention to detail.
• Must be a self-starter, able to independently drive tasks to completion and willing to ramp up on new IP domains through documentation and hands-on debug.

Responsibilities

• Executing and contributing to post-silicon validation efforts for SOC-level IP blocks, including test plan development, test execution, coverage tracking, and issue reporting across program milestones
• Debugging hardware and system-level issues found during bring-up, validation, and production phases of SOC programs, with a focus on system IP blocks such as DMA engines, interrupt controllers, and data path logic
• Performing post-silicon debug analysis using scan dump tools and debug reports to investigate hangs, stalls, and error conditions at the IP and system level
• Triaging failures by collecting and correlating debug data across multiple IP domains, with guidance from senior engineers on complex cross-chiplet issues
• Working with multiple teams and tracking test execution to make sure all features are validated and optimized on time
• Working closely with design, firmware, driver, software runtime, and kernel teams to understand IP behavior, error propagation, software-hardware interactions, and power management dependencies
• Developing and maintaining validation test content targeting error handling, fault injection, and power management scenarios
• Engaging in hardware/software modeling and debug frameworks to reproduce and root-cause silicon failures
• Participating in collaborative triage and debug efforts across multiple teams and IP domains, progressively taking ownership of specific IP areas

Job description

AMD is seeking a Sr. Systems Design Engineer for the Data Center GPU team in Markham, ON. You will drive post-silicon validation, debug, and cross-team collaboration to ensure high-quality IP blocks and system performance.

The role emphasizes ownership, scalable solutions, and hands-on debugging across SOC blocks. The position requires expertise in post-silicon validation, with strong C/C++/Python skills and a deep understanding of SoC architectures, DMA, and memory subsystems.