FPGA Design Engineer — High-Speed Quantum Systems

IQM Quantum Computers; Espoo; On-site; EUR 60,000 - 90,000; Full time

Job summary

IQM Quantum Computers in Espoo, Finland, is seeking an FPGA Engineer to design and implement FPGA logic for high-speed data processing and inter-subsystem communication within quantum systems. You'll join the Scalable Electronics team and work with FPGA developers, hardware and software engineers, physicists and quantum error correction experts.

You will contribute to a full-stack approach from design to validation, focusing on timing constraints and performance, while collaborating in a

Qualifications

• Design FPGA IP blocks and validate with simulation.
• At least 1 year in a professional engineering environment.
• BSc or MSc in electrical engineering, computer science, or related field.
• Able to collaborate across disciplines in a low-hierarchy setup.
• Proficient VHDL and experience with high-performance FPGA families.
• Familiar with digital logic fundamentals and clock domain concepts.

Responsibilities

• Design, implement, simulate, and benchmark FPGA IP blocks in VHDL.
• Integrate IP blocks to form a complete design.
• Plan and evaluate different solutions with the team.
• Benchmark and optimize data throughput, latency, and resources.
• Align interfaces with software, firmware, and hardware stakeholders.
• Share knowledge across domain experts and keep tooling healthy.

Skills

FPGA IP design

VHDL

1 year experience

Digital logic

Clock domains

Cross-disciplinary

Education

BSc/MSc in electrical engineering, computer science, or related field

Tools

Intel/Altera FPGAs

Quartus

Job description

IQM Quantum Computers in Espoo, Finland, is seeking an FPGA Engineer to design and implement FPGA logic for high-speed data processing and inter-subsystem communication within quantum systems. You'll join the Scalable Electronics team and work with FPGA developers, hardware and software engineers, physicists and quantum error correction experts.

You will contribute to a full-stack approach from design to validation, focusing on timing constraints and performance, while collaborating in a