Verifizierungsspezialist : in

IC Resources; Madrid; Presencial; EUR 55.000 - 75.000; Jornada completa

Descripción de la vacante

A leading technology recruitment firm in Spain is seeking a Senior Functional Verification Engineer to join the Verification Team. In this role, you will ensure the correctness and functionality of complex digital designs using advanced verification methodologies and tools. The ideal candidate will have industry experience in functional verification and expertise in SystemVerilog, UVM, and various scripting languages. The company offers competitive compensation and a supportive work environment.

Servicios

Flexible work environment

Competitive compensation

Culture of continuous learning and growth

Formación

• Significant industry experience in functional verification.
• Hands-on experience with simulation tools and methodologies.
• A solid understanding of formal and dynamic verification techniques.

Responsabilidades

• Develop and execute verification plans to ensure functionality and correctness.
• Utilise SystemVerilog and UVM methodologies for validation.
• Perform formal and dynamic verification to resolve design issues.
• Leverage scripting languages for automation.
• Manage version control and troubleshoot technical challenges.

Conocimientos

SystemVerilog

UVM methodologies

Python

Perl

Bash

TCL

Version control

Educación

Master’s or PhD in a relevant field

Herramientas

Simulation tools

Regression tools

Git

SVN

Descripción del empleo

My client is looking for a Senior Functional Verification Engineer to join their dynamic Verification Team. In this role, you will be at the forefront of ensuring the correctness and functionality of complex digital designs at the Register Transfer Level (RTL). Using advanced verification methodologies and tools, you will play a pivotal role in validating designs that shape the future of technology.

They offer a flexible and supportive work environment, competitive compensation, and a culture of continuous learning and growth.

Responsibilities

As a Senior Functional Verification Engineer, you will :

• Develop and execute verification plans to ensure the functionality and correctness of digital designs
• Utilise SystemVerilog and UVM methodologies to validate designs at the block, sub-system, and top levels
• Perform both formal and dynamic verification to identify and resolve design issues
• Leverage scripting languages (Python, Perl, Bash, TCL)
• Utilise simulation tools and regression methodologies to validate designs
• Manage version control using tools like Git and SVN
• Troubleshoot and resolve complex technical challenges with a keen eye for detail

Qualifications

To excel in this role, you should have :

• A Master’s or PhD in a relevant field
• Significant industry experience in functional verification
• Expertise in SystemVerilog and UVM methodologies
• Strong knowledge of scripting languages (Python, Perl, Bash, TCL) and regression tools
• Hands‑on experience with simulation tools and methodologies
• A solid understanding of formal and dynamic verification techniques

If you’re ready to take your career to the next level and make a significant impact in the world of digital design, we want to hear from you. Apply today and become a part of this innovative team.