Senior FPGA Engineer — ISAC & ML on RFSoC (Madrid)

Fundación IMDEA Networks; Madrid; Presencial; EUR 75.000 - 110.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

A leading role in flagship internal项目

International research environment

State-of-the-art RF and FPGA lab

Competitive compensation package

Descripción de la vacante

IMDEA Networks Institute in Madrid seeks a Senior FPGA Engineer to lead FPGA design for the ISAC prototyping platform. You will drive RTL development, ISAC accelerator blocks, and ML-augmented inference on FPGA fabrics.

The role requires 7+ years in FPGA design, strong VHDL/SystemVerilog, and experience with Xilinx RFSoC and Vivado/Vitis. Collaboration with ARM CPUs and lab teams is essential.

Formación

• MSc or PhD in Telecommunications, Electrical Engineering, Computer Science or related field.
• At least 7 years of professional FPGA design experience.
• Strong RTL design skills in VHDL and SystemVerilog.
• Solid experience with Xilinx RFSoC and UltraScale+ devices and the Vivado and Vitis toolchain.
• Experience with high throughput AXI based datapaths, on chip memory hierarchies and timing closure.
• Solid background in DSP for wireless physical layers (OFDM, channel estimation, channel coding, beamforming).
• Prior experience with wireless experimentation platforms or software defined radios is a strong plus.
• Experience with FPGA implementation of neural networks is a plus.
• Proficiency in written and spoken English.

Responsabilidades

• Lead the architecture, RTL design and continuous evolution of the FPGA fabric of the platform.
• Implement ISAC accelerators directly on the FPGA, including high resolution channel estimation and processing.
• Integrate sparse and spiking neural networks for low latency edge processing.
• Co-design hardware blocks with software on embedded ARM cores and host servers.
• Drive platform integration with mm-wave and sub-THz front ends.
• Mentor junior engineers and PhD students; contribute to open source releases.

Conocimientos

VHDL

SystemVerilog

DSP for wireless

English proficiency

Educación

MSc or PhD in Telecommunications, Electrical Engineering, or Computer Science

Herramientas

Vivado

Vitis

Xilinx RFSoC

UltraScale+ devices

Descripción del empleo

IMDEA Networks Institute in Madrid seeks a Senior FPGA Engineer to lead FPGA design for the ISAC prototyping platform. You will drive RTL development, ISAC accelerator blocks, and ML-augmented inference on FPGA fabrics.

The role requires 7+ years in FPGA design, strong VHDL/SystemVerilog, and experience with Xilinx RFSoC and Vivado/Vitis. Collaboration with ARM CPUs and lab teams is essential.