FPGA / RTL Design Engineering Intern (VHDL, Verilog, SystemVerilog) – Barcelona

Keysight Technologies, Inc.; Barcelona; On-site; EUR 6,700 - 11,000; Full time

Job summary

Keysight Technologies seeks a highly motivated FPGA/RTL Design Engineering Intern to join our engineering team in Barcelona, Spain, contributing to the development of high-performance FPGA-based systems.

This internship is ideal for students passionate about digital hardware design, offering hands-on FPGA development and collaboration with international teams using Vivado, Quartus, and real FPGA hardware such as Zynq UltraScale+.

Qualifications

• Currently enrolled in a Bachelor’s or Master’s degree in Digital Electronics, Electrical Engineering, Telecommunications Engineering, Computer Engineering or a related field.
• Must remain enrolled for the full duration of the internship and university must sign convenio de prácticas with Keysight.
• Fluent English (B2-C1 or higher), spoken and written; daily use with international colleagues.

Responsibilities

• Design and implement RTL for FPGA-based systems using VHDL, Verilog or SystemVerilog
• Develop and execute testbenches for functional verification
• Work with FPGA toolchains (AMD/Xilinx Vivado, Intel/Altera Quartus) from synthesis to implementation
• Integrate, debug and validate designs on real FPGA hardware (e.g. Zynq UltraScale+, RFSoC or similar platforms)
• Analyze and optimize designs for timing closure, latency and resource utilization
• Collaborate with engineers on digital signal processing (DSP), high-speed interfaces and system integration

Skills

FPGA development

RTL design

Digital hardware

English fluency

Education

Bachelor’s or Master’s in Digital Electronics / Electrical / Telecommunications / Computer Engineering

Tools

Vivado

Quartus

ModelSim

QuestaSim

Job description

Overview

Keysight is a mission-critical design enablement partner for organizations solving the world’s most complex engineering challenges. With deep engineering expertise and leading design, emulation, and test solutions, our ~16,800 employees help customers in over 100 countries accelerate innovation across communications, automotive, energy, quantum, aerospace and defense, semiconductor, and artificial intelligence markets. Learn more about what we do.

At Keysight, people come together to explore new ideas, challenge what's possible, and advance the technologies defining the future. Here, you'll find opportunities to do your best work, take your career further, and thrive in an award-winning culture. Learn more about our benefits.

Keysight is looking for a highly motivated FPGA / RTL Design Engineering Intern (VHDL / Verilog / SystemVerilog) to join our engineering team in Barcelona, Spain, and contribute to the development of high-performance FPGA-based systems.

This internship is ideal for students passionate about digital hardware design, working close to silicon, and building real digital systems used in advanced test and measurement solutions.

Responsibilities

• Design and implement RTL for FPGA-based systems using VHDL, Verilog or SystemVerilog
• Develop and execute testbenches for functional verification
• Work with FPGA toolchains (AMD/Xilinx Vivado, Intel/Altera Quartus) from synthesis to implementation
• Integrate, debug and validate designs on real FPGA hardware (e.g. Zynq UltraScale+, RFSoC or similar platforms)
• Analyze and optimize designs for timing closure, latency and resource utilization
• Collaborate with engineers on digital signal processing (DSP), high-speed interfaces and system integration

Qualifications

• Currently enrolled in a Bachelor’s or Master’s degree in Digital Electronics, Electrical Engineering, Telecommunications Engineering, Computer Engineering or a related field
• Must remain enrolled for the full duration of the internship, and your university must be able to sign an internship agreement (convenio de prácticas) with Keysight
• Fluent English (B2-C1 or higher), spoken and written. You will use English every day to work with international colleagues and teams.
• Hands-on experience with FPGA development
• Experience writing RTL (VHDL, Verilog or SystemVerilog)
• Experience with simulation and testbench environments (ModelSim, QuestaSim or similar simulators)
• Familiarity with FPGA tools such as Vivado or similar
• Experience implementing and validating designs on real FPGA hardware

Candidates must be able to demonstrate at least one end-to-end FPGA project beyond standard coursework (design -> simulation -> implementation -> validation), for example a final thesis (TFG/TFM), research, competition or personal project.

Nice to have:

• Knowledge of AXI / AXI4 / AXI-Stream interfaces
• Experience with SoC FPGA platforms (Zynq, RFSoC)
• Background in signal processing, DSP or RF systems
• Experience with timing closure and optimization
• Programming languages: Python, C++
• Hands-on experience with hardware (HW) set-up and lab debugging (e.g. oscilloscope, logic analyzer)

Additional information:

This role does not offer visa sponsorship. Candidates must already be legally able to do an internship in Spain at the time of application.