Digital IC Design Lead Engineer

Innova IRV Microelectronics; Málaga; Presencial; EUR 90.000 - 130.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Flexible paid time off

Disability accommodation assistance

Descripción de la vacante

Innova IRV Microelectronics, based in Málaga, seeks a Digital IC Design Lead Engineer to drive architecture, RTL design and integration for next‑generation RISC‑V SoCs. You will lead a team of Digital IC Design Engineers, shaping pipelines, memory hierarchies and IP integration while coordinating with verification and silicon bring‑up teams.

The ideal candidate has 7+ years in digital IC/ASIC design, strong Verilog/SystemVerilog expertise and a track record of RISC‑V projects.

Formación

• 7+ years of experience in digital IC or ASIC design.
• Master’s degree in electronic engineering, computer engineering, microelectronics or related semiconductor focus.
• Demonstrated experience delivering multiple ASIC/SoC developments from specification to silicon.
• Experience leading technical teams or acting as technical lead on complex semiconductor projects.
• Proven track record in RISC‑V processor or subsystem development.
• Experience integrating complex SoCs with CPUs, accelerators, memories and IPs.
• Expert knowledge on Verilog and SystemVerilog RTL design.
• RISC‑V ISA and related architecture knowledge including debug, MMU and caches.
• Experience with synthesis, STA, CDC/RDC analysis, low‑power techniques and DFT concepts.
• Experience with FPGA prototyping and HW bring‑up.
• Proficiency with EDA tools and scripting for automation.

Responsabilidades

• RISC-V SoC components architecture and RTL design leadership across teams.
• Own IP and subsystem development lifecycle from spec to product release.
• Lead multiple projects, plan priorities, manage risks and deliverables.
• Mentor and develop Digital IC Design Engineers through reviews and coaching.
• Define robust verification strategies with coverage goals.
• Oversee integration of cores, accelerators, memory subsystems and IPs.
• Drive timing, power, area targets and testability improvements.
• Lead post‑silicon debug, root‑cause analysis and design improvements.
• Establish digital design methodologies, coding standards and automation.

Conocimientos

RISC-V architecture leadership

RTL design expertise

Scripting (Python/Tcl)

EDA tools proficiency

Team leadership

Open-source RISC-V experience

Educación

Master's degree in Electronic Engineering / Microelectronics

PhD in Electronic Engineering / Microelectronics (Desirable)

Herramientas

Synopsys

Cadence

Siemens

Descripción del empleo

As a Digital IC Design Lead Engineer at Innova IRV Microelectronics, you will join our engineering team based in Málaga, working together to shape next-generation chip solutions. You will lead the architecture, RTL design, integration and implementation of digital IPs and subsystems for next-generation RISC-V SoC platforms. The role combines hands‑on technical expertise with Digital IC Design Engineers leadership, ensuring designs meet functional, performance, power, area, quality and schedule objectives. If you excel driving engineering practices across the digital design lifecycle from specification and microarchitecture through RTL development, verification support, synthesis, silicon bring‑up and product release and want to contribute to innovative microelectronics development from Málaga, we encourage you to apply.

Key Responsibilities

• RISC-V SoC components architecture, microarchitecture and RTL design leadership, optimizing performance, power, area, scalability and quality while complying with RISC‑V standards
• IPs and subsystems complete development lifecycle ownership from specification and RTL implementation till product release, through synthesis, integration and silicon bring‑up
• Successful execution of multiple concurrent development projects, planning, prioritizing and monitoring technical activities, schedules, risks and deliverables
• Lead, mentor and develop a team of Digital IC Design Engineers, fostering technical excellence, collaboration, continuous learning and high engineering standards through coaching, design reviews and performance management
• Partnering with verification team to define robust verification strategies, ensuring functional coverage, design issues resolution achieving first‑pass silicon success
• Oversee integration of RISC‑V cores, accelerators, memory subsystems, peripherals and third‑party IP, ensuring interoperability, robust interface implementation and compliance with clock, reset and power domain requirements
• Cross‑teams collaboration to achieve timing closure, power and area targets, manufacturability and testability through RTL optimization and implementation support
• Lead post‑silicon debug, root‑cause analysis and design improvements, supporting product qualification and future silicon revisions
• Establish and continuously improve digital design methodologies, coding standards, automation, design reuse and engineering best practices to increase team productivity and design quality

Minimum Knowledge and Experience

• 7+ years of experience in digital IC or ASIC design.
• Master’s degree in electronic engineering, Computer Engineering, Microelectronics or other discipline with focus on semiconductor design.
• Demonstrated experience delivering multiple ASIC or SoC developments from specification to silicon
• Experience leading technical teams or acting as technical lead on complex semiconductor projects
• Proven track record in RISC‑V processor or subsystem development
• Experience integrating complex SoC containing CPUs, accelerators, memories and peripheral IPs
• Expert knowledge on Verilog and SystemVerilog RTL design
• RISC‑V ISA, privileged architecture, exception handling, interrupts, MMU, caches and debug architecture strong understanding
• Experience designing high‑performance pipelines, memory hierarchies, and coherent interconnects
• Deep understanding of synthesis, STA, CDC/RDC analysis, linting and low‑power methodologies
• Knowledge of Design for Test (DFT) concepts and integration
• Experience with FPGA prototyping and hardware bring‑up
• Proficiency with industry‑standard EDA tools (Synopsys, Cadence or Siemens)
• Scripting skills in Python, Tcl, Bash or Perl for design automation

Desired Knowledge and Experience

• PhD in Electronic Engineering, Computer Engineering, Microelectronics or other discipline with focus on semiconductor design
• Experience with open‑source RISC‑V ecosystem and commercial RISC‑V cores
• Vector, AI/ML, DSP or security extensions knowledge
• Coherent interconnects experience
• Familiar with hardware security features, including secure boot, cryptographic accelerators, trusted execution environment and root‑of‑trust architectures
• Experience with functional safety and security standards (ISO 26262, IEC 61508, DO‑254 or Common Criteria)
• Exposure to chiplet‑based architectures and advanced packaging technologies
• Experience managing external IP vendors and semiconductor foundry interactions
• Technical leadership with ability to influence architectural decisions
• Strong people management, coaching and mentoring skills
• Excellent project planning and execution capabilities
• Ability to communicate effectively with technical and executive stakeholders
• Strategic thinking combined with strong execution focus
• Excellent analytical and problem‑solving skills
• Collaborative mindset with experience leading cross‑functional engineering organizations
• Commitment to engineering excellence, continuous improvement and innovation

What we offer

• Innova IRV Microelectronics is proud to be an equal employment opportunity workplace. We offer a competitive compensation package based on experience that includes flexible paid time off; …
• We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.