Digital ASIC Design Engineer

IC Resources; Barcelona; Presencial; EUR 50.000 - 70.000; Jornada completa

Descripción de la vacante

A leading semiconductor company in Barcelona is seeking a Digital ASIC Design Engineer. In this role, you will work on cutting-edge technology including RISC-V designs and machine learning applications. The ideal candidate should have a degree in Electronics or a related field and substantial experience in ASIC or FPGA design projects. Visa sponsorship and relocation support can be offered if required.

Servicios

Visa sponsorship

Relocation support

Formación

• Strong experience in ASIC / FPGA design projects is essential.
• Knowledge of RISC‑V / CPU / GPU is a bonus.
• Familiarity with PCIe protocols is advantageous.

Responsabilidades

• Contribute to advanced technology nodes and RISC‑V designs.
• Work on CPU architecture and machine learning applications.

Conocimientos

ASIC / FPGA design projects

UVM environments & processes

System Verilog

C / C++

Python

Educación

Degree in Electronics / Microelectronics

Descripción del empleo

Digital ASIC Design Engineer - Barcelona

Exciting opportunity to work on the latest cutting edge technology in the semiconductor industry.

In this new role as senior digital design engineer you will have the opportunity to contribute to advanced technology nodes, consisting of RISC‑V designs, CPU architecture, PCIe protocols and machine learning.

I am looking to speak with senior digital design engineers - who have experience of, or an interest in :

• Degree in Electronics / Microelectronics or similar field
• Strong experience in ASIC / FPGA design projects
• UVM environments & processes
• System Verilog for IP / SOC design of digital ICs / ASIC IP or chips
• Complex ASIC / FPGA designs & architecture for advanced technology nodes
• RISC‑V / CPU / GPU knowledge (is a bonus, but not required)
• PCIe knowledge (also a bonus skill)
• scripting / coding skills - C / C++, Python etc.
• Visa sponsorship and relocation support can be offered if required.