Senior FPGA Lead & Architect for Ultra-High-Speed Ethernet

Teledyne FLIR; Kongens Lyngby; Presencial; DKK 900.000 - 1.200.000; Jornada completa

Descripción de la vacante

Teledyne LeCroy Xena seeks a highly skilled FPGA lead/architect at its Lyngby office to drive the next-generation high-speed FPGA platform. You will define architecture, lead RTL design and implementation, and collaborate across engineering functions to deliver scalable, ultra-fast Ethernet solutions.

The role demands 8–10 years of FPGA experience, strong VHDL/Verilog/SystemVerilog skills, and interactions with vendors. Danish language is a plus; English proficiency is essential.

Formación

• 8–10 years’ experience in leading advanced, high-speed FPGA architecture, design and implementation.
• Experience with architecting and developing large systems.
• Experience with FPGA architecture and high-speed design (VHDL/Verilog/SystemVerilog).
• Experience with synthesis and simulation (preferably Xilinx Vivado).
• Experience with data communication, high-speed Ethernet interfaces in particular.
• Good English skills (written and spoken); Danish is an advantage.

Responsabilidades

• Define feature requirements at architectural level and oversee RTL design and implementation.
• Lead FPGA design efforts from concept to deployed platform.
• Collaborate with cross-functional engineering teams to optimize architecture and performance.
• Mentor junior engineers and drive technical decisions.
• Engage with FPGA vendors and test equipment teams to validate next-generation solutions.

Conocimientos

High-speed FPGA design

FPGA architecture

VHDL/Verilog/SystemVerilog

Synthesis and simulation

Python scripting

Ethernet tech

Network protocols

English proficiency

Danish language (advantage)

Educación

Bachelor’s or Master’s in electronics

Herramientas

Xilinx Vivado

Descripción del empleo

Teledyne LeCroy Xena seeks a highly skilled FPGA lead/architect at its Lyngby office to drive the next-generation high-speed FPGA platform. You will define architecture, lead RTL design and implementation, and collaborate across engineering functions to deliver scalable, ultra-fast Ethernet solutions.

The role demands 8–10 years of FPGA experience, strong VHDL/Verilog/SystemVerilog skills, and interactions with vendors. Danish language is a plus; English proficiency is essential.