Quantum FPGA/ASIC Design Engineer – On-site Copenhagen

Techjob; København; Hybrid; DKK 700,000 - 950,000; Full time

Job summary

Celare Quantum Communications, based in Copenhagen, seeks an experienced FPGA/ASIC design engineer to drive high‑speed data processing and early ASIC development. You will work on architecture, RTL, and verification in a small, agile team closely connected to academic research.

The role involves designing for high‑speed interfaces, IP core integration, and lab bring-up, with opportunities to influence product deployment across global quantum‑communication projects.

Qualifications

• MSc in electrical engineering or similar.
• 5+ years of hands-on FPGA/ASIC design experience, including IP core integration, FPGA timing closure, and floorplanning.
• Proficiency in Verilog/SystemVerilog (or VHDL).
• Experience with ASIC-grade verification (UVM, constrained-random, coverage-driven).
• Experience implementing high-speed data processing on complex FPGAs (AMD/Xilinx UltraScale+).
• Experience with high-speed interfaces like PCIe, JESD204B/C, and multi-gigabit transceivers.
• Scripting in Tcl, Bash, and Python.
• Good understanding of high-speed signal integrity.

Responsibilities

• Contributing to the early stages of ASIC design, from architecture to RTL.
• Designing and implementing high-speed data processing systems on FPGAs.
• Developing self-checking testbenches and verification environments for FPGA/ASIC designs.
• Developing and integrating IP cores.
• Participating in system-level integration.
• Bringing up, testing, and debugging hardware in the lab.

Skills

FPGA/ASIC design

Verilog/SystemVerilog

ASIC verification (UVM)

High-speed FPGA data

PCIe/JESD interfaces

Scripting (Python/Tcl)

Timing closure

IP core integration

Education

MSc in electrical engineering

Job description

Celare Quantum Communications, based in Copenhagen, seeks an experienced FPGA/ASIC design engineer to drive high‑speed data processing and early ASIC development. You will work on architecture, RTL, and verification in a small, agile team closely connected to academic research.

The role involves designing for high‑speed interfaces, IP core integration, and lab bring-up, with opportunities to influence product deployment across global quantum‑communication projects.