FPGA/ASIC Design Engineer

Techjob; København; Hybrid; DKK 700,000 - 950,000; Full time

Job summary

Celare Quantum Communications, based in Copenhagen, seeks an experienced FPGA/ASIC design engineer to drive high‑speed data processing and early ASIC development. You will work on architecture, RTL, and verification in a small, agile team closely connected to academic research.

The role involves designing for high‑speed interfaces, IP core integration, and lab bring-up, with opportunities to influence product deployment across global quantum‑communication projects.

Qualifications

• MSc in electrical engineering or similar.
• 5+ years of hands-on FPGA/ASIC design experience, including IP core integration, FPGA timing closure, and floorplanning.
• Proficiency in Verilog/SystemVerilog (or VHDL).
• Experience with ASIC-grade verification (UVM, constrained-random, coverage-driven).
• Experience implementing high-speed data processing on complex FPGAs (AMD/Xilinx UltraScale+).
• Experience with high-speed interfaces like PCIe, JESD204B/C, and multi-gigabit transceivers.
• Scripting in Tcl, Bash, and Python.
• Good understanding of high-speed signal integrity.

Responsibilities

• Contributing to the early stages of ASIC design, from architecture to RTL.
• Designing and implementing high-speed data processing systems on FPGAs.
• Developing self-checking testbenches and verification environments for FPGA/ASIC designs.
• Developing and integrating IP cores.
• Participating in system-level integration.
• Bringing up, testing, and debugging hardware in the lab.

Skills

FPGA/ASIC design

Verilog/SystemVerilog

ASIC verification (UVM)

High-speed FPGA data

PCIe/JESD interfaces

Scripting (Python/Tcl)

Timing closure

IP core integration

Education

MSc in electrical engineering

Job description

Celare Quantum Communications is a Danish high-tech quantum technology company with a mission to radically improve cybersecurity and enable trusted global data sharing.

Our core product is Continuous-Variable Quantum Key Distribution (CV-QKD), a unique, cutting‑edge technology born from years of university research. This technology enables quantum‑secure key exchange for protecting sensitive data across critical infrastructure.

Celare partners with national and international governments, telecom operators, data centers, banks, defense ministries, and leading academic institutions. Over the past year, our team has launched commercial pilot deployments of our technology.

The Celare Team
We are a highly specialized and ambitious team of quantum engineers, serial entrepreneurs, mathematicians, software engineers, IC and FPGA designers, and specialists in lasers, RF, and electronics.

Based in Copenhagen, we combine deep academic expertise with practical experience in launching complex, high‑impact technology products.

The Role
In this role, you will get a unique opportunity to work at the cutting edge of quantum technology development. You will join our FPGA/ASIC team and work directly with FPGA design for high‑speed data processing, testbench development, and the early stages of our ASIC development.

As part of a small and agile organization, you will contribute across the full product lifecycle — from early architectural decisions and prototyping to production and large‑scale deployment. You will work both in collaboration with our team and independently as a specialist, sharing knowledge across disciplines.

This is a hands‑on role with real responsibility and influence. It offers the chance to work in a dynamic, international, multilingual, and multicultural team with direct connections to academic research and state‑of‑the‑art technologies.

The role is based on‑site at our Copenhagen headquarters.

Responsibilities

• Contributing to the early stages of ASIC design, from architecture to RTL
• Designing and implementing high‑speed data processing systems on FPGAs
• Developing self‑checking testbenches and verification environments for FPGA/ASIC designs
• Developing and integrating IP cores
• Participating in system‑level integration
• Bringing up, testing, and debugging hardware in the lab

Qualifications

• MSc in electrical engineering or similar
• 5+ years of hands‑on FPGA/ASIC design experience, including IP core integration, FPGA timing closure, and floorplanning
• Proficiency in Verilog/SystemVerilog (or VHDL)
• Experience with ASIC‑grade verification, e.g., UVM, constrained‑random and coverage‑driven testing, SystemVerilog Assertions, and bit‑accurate reference models
• Experience implementing high‑speed data processing on complex FPGAs (e.g., AMD/Xilinx UltraScale+) and their toolchains
• Experience with high‑speed interfaces such as PCIe, JESD204B/C, and multi‑gigabit transceivers
• Proficiency in scripting, e.g., Tcl, Bash, and Python
• Good understanding of high‑speed signal integrity

Nice to have

• Experience with ASIC design flows, e.g., synthesis, static timing analysis, DFT, and gate‑level simulation
• Experience with high‑speed board design (schematic design, PCB layout, integration, and power delivery)

We Offer
This full‑time position offers the opportunity to build and shape the future of quantum communication in collaboration with an experienced and dynamic team. We provide individual growth plans aligned with your personal preferences and motivation. We offer competitive compensation commensurate with qualifications and experience.

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