SoC Physical Design Verification Engineer (M, F, D)

Lex; München; Vor Ort; EUR 90.000 - 120.000; Vollzeit

Zusammenfassung

Apple in Munich is seeking a driven engineer to join the Silicon Technologies group and help verify next-generation SOCs. You will work with the Physical Design team to understand chip architecture and drive physical verification early in the design cycle.

Responsibilities include DRC/LVS, collaboration with package and floorplan teams, and guiding verification with standard tools like Mentor Calibre; English fluency is required.

Qualifikationen

• MSEE required.
• Fluent in English (spoken and written).

Aufgaben

• Work on full chip DRC and LVS, including PNR tools, ERC, and high voltage check.
• Collaborate with the physical design team to streamline verification and develop guidelines.
• Support partition owners with physical verification activities and plan work.
• Resolve design and flow issues related to physical design and drive execution.
• Collaborate with the package and floor-plan teams.

Kenntnisse

English language proficiency

Ausbildung

Master of Science in Electrical Engineering

Jobbeschreibung

Summary

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions. Joining this group means you’ll be crafting and building the technology that fuels Apple’s devices. Together, we enable our customers to do all the things they love with their devices. In this highly visible role, you will be a critical part of a growing team responsible for physical verification of SOC's in Munich, Germany.

Join us!

Description

Work with Physical Design team to understand chip architecture and drive physical verification aspects early in design cycle.

Responsibilities

• Work on full chip DRC and LVS (including understanding of the PNR tools, ERC, high voltage check);
• Work with physical design team, drive methodologies and “best known methods” to streamline physical design work, come up with guidelines and checklists, drive execution, and supervise progress while offering physical verification support;
• Support partition owners with Physical Verification activities, set goals, plan short and long-term work;
• Resolve design and flow issues related to physical design, identify potential solutions and drive execution;
• Collaborate with the package and floor-plan teams.

Minimum Qualifications

• Graduate in MSEE.
• Ability to fluently speak and write in English.

Preferred Qualifications

• Familiar with hierarchical design approach, top-down design.
• Experience with padring, bump, RDL design.
• Familiar with GDS assembly, GDS requirements for hard macros.
• Analog/Digital Layout design background and experience is a plus.
• Experienced in industry standard tools used for physical verification such as Mentor Calibre as well as collaborating with foundries.
• Familiar with TCL scripting.

At Apple, we're not all the same. And that's our greatest strength. We draw on the differences in who we are, what we've experienced, and how we think. Because to create products that serve everyone, we believe in including everyone. Therefore, we are committed to treating all applicants fairly and equally. We will work with applicants to make any reasonable accommodations.

At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.

Learn about accessibility in Apple’s workplace

Role Number: 200661327-1731