SOC Physical Design Engineer (M, F, D)

Lex; München; Vor Ort; EUR 90.000 - 150.000; Vollzeit

Zusammenfassung

Apple in Munich is seeking an experienced Digital Physical Design Engineer to own block level PnR, floor-planning, clock and power distribution for a next‑gen SoC.

You will drive static timing closure, perform power/EM/IR drop and layout verification, and contribute to guidelines and specs to ensure on-time tape-out.

Candidates should have a strong background in PnR using Synopsys or Cadence tools, Verilog knowledge a plus, and a track record in large, high-frequency designs.

Qualifikationen

• MSEE or equivalent degree required.
• Hands-on experience with Place & Route tools (Synopsys/Cadence) and understanding of their capabilities.
• Scripting and programming with Perl, TCL, and Make.
• Experience with large, high-frequency SoC designs is preferred.

Aufgaben

• Own block-level PnR implementation from netlist to final GDS.
• Lead floor-planning, clock and power distribution for the SoC.
• Perform static timing analysis and power integrity checks.
• Coordinate with verification and layout teams to meet schedule.

Kenntnisse

PnR tools expertise

Clock/Power distribution understanding

Static timing analysis

Verilog knowledge

Scripting: Perl/Tcl/Make

Ausbildung

MSEE or equivalent

Tools

Synopsys

Cadence

Jobbeschreibung

Summary

Imagine what you could do here. At Apple, new ideas have a way of becoming great products very quickly. Do you want to bring passion and dedication to your job? There's no telling what you could accomplish at Apple. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices — we continue to strengthen our commitment to leave the world better than we found it. By now the industry is accustomed to Apple taping out the SoCs for our various products at a rigorous pace. In order to achieve this, our world-class design processes are driven by our top-notch Physical Design engineers. Are you a classic partition PnR engineer recognised in the industry for the knowledge in standards and practices in Physical Design? Do you have strong track record with recent successful tape-outs in deep sub-micron technology? As SoC Digital Physical Design Engineer, you will take part in the large scale SoC physical design cycle from netlist to tape-out, including full flow of back-end implementation and verification always meeting schedule and design goals.

Are you ready to join some of the world's leading engineers, and help us deliver the next generation of ground-breaking Apple products?

Join Us!

Description

You are going to own block level PnR, floor-planning, clock and power distribution

You will get involved with static timing closure with commercial tools

You will do power and noise analysis (EM / IR-Drop / Xtalk) as well as layout verification (DRC / LVS)

You will be developing and validating dedication low power clock network guidelines

With phenomenal focus you will resolve design and flow issues related to physical design and identify potential solutions whilst driving execution

You know what documentation should look like, and will help with guidelines and specs

Responsibilities

• As a member of our Physical Design team in this highly transparent role, you will directly own implementation of design partition(s) (Netlist to delivery of our final GDS) for a highly complex SoC using brand-new process technology

Minimum Qualifications

• You hold a MSEE or equivalent strong experience.
• We will be counting on your expertise and years of hands on experience with one of the Place & Route ('PnR') tools available today (Synopsys / Cadence), and having understanding of their capabilities and underlying algorithms.
• You can do scripting and programming using several of the following: Perl, TCL and Make.

Preferred Qualifications

• We expect experience with large SoC designs (>20M gates) with frequencies in excess of 1GHZ and beyond.
• If you also have working knowledge in Verilog, that is a huge plus for us.
• Your communication skills are excellent, and like the rest of us here at Apple you love working in open and multi-cultural environment.
• You are familiar with hierarchical design approach, top-down design, and timing and physical convergence.
• You are demonstrating in-depth understanding of static-timing analysis, extensive know-how in clock/power distribution and analysis, as well as RC extraction and correlation.
• You have experience with SoC practices such as multiple voltage and clock domains, integration of mixed-signal IPs and I/O integration.

At Apple, we're not all the same. And that's our greatest strength. We draw on the differences in who we are, what we've experienced, and how we think. Because to create products that serve everyone, we believe in including everyone. Therefore, we are committed to treating all applicants fairly and equally. We will work with applicants to make any reasonable accommodations.

At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.

Learn about accessibility in Apple’s workplace

Role Number: 200642449-1731