SoC Physical Design Verification Engineer (M, F, D)

Apple Inc.; München; Hybrid; EUR 90.000 - 130.000; Vollzeit

Zusammenfassung

Apple Inc. in Munich is seeking a SoC Physical Design Verification Engineer to contribute to the physical verification of SOCs within the Silicon Technologies group.

You will collaborate with the physical design, package and floor-plan teams to ensure robust verification methodologies and successful integration of complex chips. The role requires a Master’s degree in Electrical Engineering and full professional English proficiency, with hands-on experience in industry standard verification flows

Qualifikationen

• Graduate in MSEE.
• Ability to fluently speak and write in English.

Aufgaben

• Work on full chip DRC and LVS (including understanding of the PNR tools, ERC, high voltage check).
• Drive methodologies and create guidelines and checklists to streamline physical verification work; supervise progress.
• Support partition owners with Physical Verification activities; set goals and plan short/long-term work.
• Resolve design and flow issues related to physical design and drive execution.
• Collaborate with the package and floor-plan teams.

Kenntnisse

English fluency

Ausbildung

MSEE

Tools

Mentor Calibre

TCL scripting

GDS assembly

Jobbeschreibung

SoC Physical Design Verification Engineer (M, F, D)

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions. Joining this group means you’ll be crafting and building the technology that fuels Apple’s devices. Together, we enable our customers to do all the things they love with their devices. In this highly visible role, you will be a critical part of a growing team responsible for physical verification of SOC's in Munich, Germany.Join us!

Description

Work with Physical Design team to understand chip architecture and drive physical verification aspects early in design cycle.

Responsibilities

• Work on full chip DRC and LVS (including understanding of the PNR tools, ERC, high voltage check);
• Work with physical design team, drive methodologies and “best known methods” to streamline physical design work, come up with guidelines and checklists, drive execution, and supervise progress while offering physical verification support;
• Support partition owners with Physical Verification activities, set goals, plan short and long-term work;
• Resolve design and flow issues related to physical design, identify potential solutions and drive execution;
• Collaborate with the package and floor-plan teams.

Minimum Qualifications

• Graduate in MSEE.
• Ability to fluently speak and write in English.

Preferred Qualifications

• Familiar with hierarchical design approach, top-down design.
• Experience with padring, bump, RDL design.
• Familiar with GDS assembly, GDS requirements for hard macros.
• Analog/Digital Layout design background and experience is a plus.
• Experienced in industry standard tools used for physical verification such as Mentor Calibre as well as collaborating with foundries.
• Familiar with TCL scripting.

At Apple, we're not all the same. And that's our greatest strength. We draw on the differences in who we are, what we've experienced, and how we think. Because to create products that serve everyone, we believe in including everyone. Therefore, we are committed to treating all applicants fairly and equally. We will work with applicants to make any reasonable accommodations.

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