Senior Software Compute Architect (f/m/d)

Black Semiconductor GmbH; Aachen; Vor Ort; EUR 120.000 - 190.000; Vollzeit

Zusammenfassung

Black Semiconductor GmbH seeks a Senior Software Compute Architect to own software architecture for a hybrid electronic/photonic compute engine. You will define programming models, compilers, runtimes, and workload placement to enable dynamic execution across optimal compute paths.

Collaborate with Architecture Lead and software teams to expose hybrid architecture to higher-level frameworks, driving co-design and performance optimization for AI workloads across architectures.

Qualifikationen

• Bachelor's or Master's in Computer Science, Electrical Engineering, Computer Engineering, or related field.
• 5+ years building compiler/runtime or systems software for accelerated, heterogeneous compute platforms.
• Strong compiler architecture experience, including LLVM/MLIR targeting custom accelerators.
• Experience defining instruction sets or software abstractions for novel compute architectures.
• Background in kernel and library optimization for AI workloads across hardware backends.
• Experience modeling AI workload performance across architectures (LLM training/inference).
• Understanding scale-up/scale-out systems software, workload distribution, and runtime scheduling.
• Proven ability to collaborate with hardware architects on shared interfaces and system-level design.
• Experience with compiler/runtime AI ecosystems (LLVM/MLIR, Triton, PyTorch, JAX, Python, C++, profiling tools).
• Contributions to open compiler/runtime ecosystems or firmware-level scheduling exposure are a plus.

Aufgaben

• Define the programming model, instruction abstractions, and software interfaces for exposing hybrid compute to compilers, libraries, and AI frameworks.
• Own the compiler, runtime, and library strategy to map workloads to the optimal compute path.
• Develop performance models for AI workloads to evaluate hardware/software configurations before silicon.
• Collaborate with the Hardware Compute Architect on interface contracts, telemetry, and control mechanisms for dynamic workload movement.
• Define software/firmware strategies for scale-up and scale-out execution, including workload distribution and routing.
• Prototype kernels, libraries, and runtime concepts to validate architectural decisions against AI benchmarks.

Kenntnisse

Compiler architecture

Performance modeling

AI workloads

Heterogeneous compute

Python/C++

PyTorch/JAX

System software

MLIR/Triton

Software ecosystem

Open backends

Ausbildung

Bachelor's or Master's in CS/EE

Tools

LLVM/MLIR

Triton

CUDA

oneAPI

Jobbeschreibung

The Role

We are seeking a skilled Senior Software Compute Architect at Black Semiconductor to own the software architecture enabling our next-generation hybrid electronic/photonic compute engine. You will define the programming model, compiler and runtime strategy, and workload-placement mechanisms that allow operations to dynamically execute across the most suitable compute path.

Working closely with the Architecture Lead, Senior Hardware Compute Architect, and software ecosystem teams, you will define how instructions, kernels, and libraries expose the hybrid architecture to higher-level frameworks and enable scalable execution across the platform. Your work will drive performance-focused hardware/software co-design by evaluating AI workloads across candidate architectures and guiding system-level decisions.

This role bridges compiler architecture, heterogeneous compute systems, and electronic-photonic co-design.

Responsibilities

• Define the programming model, instruction abstractions, and software interfaces that expose hybrid electronic/photonic compute capabilities to compilers, libraries, and AI frameworks.
• Own the compiler, runtime, and library strategy required to map workloads and kernels to the optimal compute path.
• Develop performance models for AI workloads, including transformer training and inference, to evaluate hardware/software configurations before silicon implementation.
• Partner with the Hardware Compute Architect to co-design interface contracts, telemetry, and control mechanisms enabling dynamic workload movement between compute paths.
• Define software and firmware strategies for scale-up and scale-out execution, including workload distribution and routing across nodes, packages, and systems.
• Prototype kernels, libraries, and runtime concepts to validate architectural decisions against real AI benchmarks.

Your Qualifications

• Bachelor's or Master's degree in Computer Science, Electrical Engineering, Computer Engineering, or a related technical field, or equivalent experience.
• 5+ years of experience building compiler, runtime, or systems software for accelerated, heterogeneous, or specialized compute platforms.
• Strong compiler architecture experience, including LLVM, MLIR, or comparable compiler infrastructure targeting custom accelerators or heterogeneous hardware.
• Experience defining instruction sets, programming models, or hardware/software abstractions for novel compute architectures.
• Strong background in kernel and library optimization for AI workloads across different hardware backends.
• Experience modeling AI workload performance, including LLM training and inference, across different hardware architectures.
• Understanding of scale-up and scale-out systems software, including workload distribution, runtime scheduling, and accelerator control-plane interactions.
• Proven ability to collaborate with hardware architects to define shared interfaces and system-level design decisions.
• Experience with compiler, runtime, and AI software ecosystems, including LLVM/MLIR, Triton, CUTLASS-style DSLs, PyTorch, JAX, Python, C++, and profiling/performance-modeling tools for architecture exploration.
• Familiarity with photonic or optical compute concepts and their impact on compiler/runtime strategies will be considered a plus.
• Experience with heterogeneous compute ecosystems such as CUDA, ROCm, Triton, oneAPI, or custom accelerator software stacks will be considered a plus.
• Contributions to open compiler or runtime ecosystems (e.g., MLIR, Triton, PyTorch backends) or exposure to firmware-level scheduling and accelerator control-plane design will be considered a plus.