Processor Design Engineer

Meyandy LLC; Deutschland; Hybrid; EUR 85.000 - 110.000; Vollzeit

Benefits dieser Stelle

Competitive salary + stock options

30+ days paid vacation

Relocation support

German social security & healthcare

Modern office

Free snacks, coffee & drinks

Zusammenfassung

Ubitium GmbH is seeking a Processor Design Engineer in Germany. The role focuses on core design areas including Cache, MMU, multi-core coherence, and branch prediction, with strong Verilog/SystemVerilog skills and preferred RISC-V experience.

Relocation is required. Currently 4 days on-site with 1 day remote. We offer a competitive salary, stock options, and a modern office environment, with relocation support available.

Qualifikationen

• Master’s degree (or equivalent) with 2+ years hands‑on experience.
• Strong Verilog/SystemVerilog skills; RISC-V experience preferred.
• Relocation required.
• 4 days on-site and 1 day remote; policy may change.

Aufgaben

• Develop processor design features in Verilog/SystemVerilog for Cores and subsystems.
• Tackle focus areas such as Cache, MMU, multi-core & bus coherence, branch prediction, and debug structures.
• Collaborate with hardware architects and verification engineers to ensure timely delivery.

Kenntnisse

Verilog/SystemVerilog

RISC-V

Ausbildung

Master's degree

Jobbeschreibung

Processor Design Engineer — Ubitium GmbH, Rülzheim.

At Ubitium, we believe the best engineering happens when people with different perspectives tackle hard problems together. We welcome applicants from all backgrounds and experiences. What matters most is curiosity, skill, and the drive to build technology that improves the world. If that resonates with you, we’d love to hear from you. Our team members come from some of the best universities in the world and left some of the largest tech companies to build something truly remarkable.

Tasks

Focus areas include but are not limited to: Cache, Memory Management Unit (MMU), Multi-Core & Bus Coherence, Branch Prediction, Debug & Test Structures.

Prospective team members require experience in at least one focus area; strong Verilog/SystemVerilog skills; RISC-V experience preferred.

Requirements

Master’s degree (or equivalent) and 2+ years of hands‑on experience in a relevant role.

Relocation required.

Currently 4 days on-site, 1 day remote.

Policy may change.

We have multiple openings.

Benefits

• Competitive salary plus stock options
• 30+ days of paid vacation
• Relocation support
• Full German social security and universal healthcare
• A modern office
• Free snacks, coffee, and drinks

Work with people who actually know their stuff – computer architects, hardware nerds, and engineers who love tough problems.

A culture where new ideas matter, but so does respect and collaboration.

Space to grow: pick up new skills, dig into areas that interest you, and shape your own path.

Get hands‑on with real implementations of AI and signal processing – not just slides or buzzwords.

An inclusive team where different perspectives are valued and everyone contributes.

We are constantly looking for talent. We recruit through multiple channels – friends & colleagues, universities and professors we know, recruiters, conventions, e‑mails and LinkedIn.