Senior Power Management IC Design Engineer

Technify Talent; Bern; Vor Ort; CHF 120.000 - 150.000; Vollzeit

Zusammenfassung

Senior Power Management IC Design Engineer sought by a semiconductor company in Switzerland (Bern). You will define architectures, then independently design transistor-level analog and power circuits for CMOS/BCD processes, and drive devices through verification and tape-out stages.

You will collaborate with cross-functional teams on layout, parasitics, and reliability, ensuring silicon bring-up and product industrialisation success.

Qualifikationen

• Master's degree or PhD in Microelectronics, Electronic Engineering, IC Design or related field.
• 5+ years hands-on analog/mixed-signal/power-management IC design experience.
• Strong experience with CMOS and preferably BCD processes.

Aufgaben

• Define power-management architectures from system requirements and specs.
• Independently design transistor-level analog and power circuits for CMOS/BCD processes.
• Design and optimize LDOs, bandgap references, op-amps, charge pumps, comparators and level shifters.
• Contribute to architecture and development of power-management and driver ICs.
• Collaborate with layout engineers on floorplanning, physical implementation and parasitic optimization.
• Perform PVT, Monte Carlo, post-layout and reliability simulations.

Kenntnisse

Power IC design

Analog/mixed-signal design

PMICs

DC-DC/AC-DC

Cadence simulations

Layout coordination

Reliability analysis

Circuit verification

Transistor-level design

Ausbildung

Master's degree in Microelectronics

PhD in Electronic Engineering

Tools

Cadence

Parasitic extraction tools

Jobbeschreibung

An established semiconductor company is looking for a Senior Power Management IC Design Engineer to play a key role in the development of advanced power-management, analog and mixed-signal ICs.

This is a high-impact opportunity for an experienced power/analog IC designer who wants to take ownership across the full IC development lifecycle, from circuit architecture and transistor-level design through layout, verification, tape-out, silicon validation and product industrialisation.

What you\'ll do as a Senior Power Management IC Design Engineer:

• Define power-management and analog/mixed-signal architectures from system requirements and product specifications.
• Independently design transistor-level analog and power circuits using CMOS and BCD technologies.
• Design and optimise key power-management blocks including LDOs, bandgap references, op-amps, charge pumps, comparators and level shifters.
• Contribute to the architecture and development of power-management and driver ICs.
• Work with layout engineers on chip/block floorplanning, physical implementation and parasitic optimisation.
• Perform PVT, Monte Carlo, post-layout and reliability simulations, including analysis of physical effects such as parasitics and IR drop.
• Collaborate with system, applications, digital, layout and test teams throughout the IC development process.
• Support tape-out, silicon bring-up, laboratory characterisation and design debugging.
• Support product industrialisation, including failure analysis, design improvements and yield optimisation.

What you\'ll bring as a Senior Power Management IC Design Engineer:

• Master\'s degree or PhD in Microelectronics, Electronic Engineering, IC Design or a related discipline.
• 5+ years\' hands-on experience in analog, mixed-signal and/or power-management IC design.
• Strong experience with CMOS and preferably BCD process technologies.
• Proven ability to independently take analog/power circuits from specification through design, verification and implementation.
• Strong understanding of analog circuit design, semiconductor device physics and IC processes.
• Experience with PMICs and/or driver ICs; DC-DC, AC-DC and power-device driver experience is highly desirable.
• Strong knowledge of Cadence-based simulation, PVT/Monte Carlo, post-layout verification and parasitic extraction.
• Experience with IC layout, floorplanning, ESD, IO, reliability and failure analysis is advantageous.
• Successful tape-out and silicon validation experience is highly desirable.
• Strong communication skills and the ability to work effectively across multidisciplinary engineering teams.