Hardware Verification Engineer — Hybrid & Growth

Siemens Mobility; Schweiz; Vor Ort; CHF 14.000 - 29.000; Vollzeit

Benefits dieser Stelle

Health and wellness benefits

Hybrid by default

Global mobility opportunities

Zusammenfassung

Siemens Industry Software invites applications for a Design Verification Engineer to join our Cairo, Egypt team. You will develop verification plans, build testbenches, and work with Questa and Veloce to validate complex DUTs.

Ideal candidates hold a B.Sc./M.Sc. in a related field with 0–3 years of hardware verification experience, SystemVerilog/UVM expertise, RTL/Verilog knowledge, and strong English communication. Proactive mentoring and collaboration across design teams are expected.

Qualifikationen

• B.Sc. or M.Sc. in Computer Engineering, Electronics and Communications Engineering, or a related field.
• Strong SystemVerilog and UVM knowledge for testbenches and assertions.
• Experience with code coverage and functional coverage techniques.
• Experience integrating VIPs into UVM environments is a plus.
• Knowledge of RTL development: Verilog; digital design and computer architecture.
• Programming knowledge: C, C++, and SystemC is a plus.
• Proficient in scripting: Perl, Shell, Tcl.
• Excellent English communication; ability to work independently and in a team.

Aufgaben

• Develop and execute verification plans, including testbench architecture and test case development.
• Design and develop co-emulation and/or simulation verification environments.
• Work with complex testbenches across platforms (simulation/co-emulation).
• Integrate software and hardware DUTs and use multiple languages in verification.
• Monitor coverage metrics to assess verification completeness.
• Run and debug testbenches on Questa and Veloce platforms.
• Collaborate with design/architecture teams to understand specs.
• Identify and debug verification issues and cover gaps.
• Mentor junior engineers and share best practices.
• Document verification progress and status to stakeholders.

Kenntnisse

SystemVerilog

UVM

Code coverage

VIP integration

RTL/Verilog

C/C++

SystemC (plus)

Scripting (Perl, Shell, Tcl)

English proficiency

Teamwork

Ausbildung

B.Sc./M.Sc. in Computer/Electronics or related

Tools

Questa

Veloce

Jobbeschreibung

Siemens Industry Software invites applications for a Design Verification Engineer to join our Cairo, Egypt team. You will develop verification plans, build testbenches, and work with Questa and Veloce to validate complex DUTs.

Ideal candidates hold a B.Sc./M.Sc. in a related field with 0–3 years of hardware verification experience, SystemVerilog/UVM expertise, RTL/Verilog knowledge, and strong English communication. Proactive mentoring and collaboration across design teams are expected.