FPGA Firmware Engineer - Level-1 Trigger (Hybrid)

SmartRecruiters, Inc.; Genf; Hybrid; CHF 71.000 - 78.000; Vollzeit

Benefits dieser Stelle

30 days paid leave

2 weeks annual closure

Health insurance through CERN scheme

CERN Pension Fund

Relocation package

Language courses

On-the-job training

Zusammenfassung

Join CERN in Geneva as a Developer for the CMS Level-1 Trigger. You will develop FPGA firmware, integrate contributions, and evaluate physics performance for a high-energy physics upgrade. You will test hardware, collaborate with CMS L1 groups, and present results at international conferences.

The role requires FPGA/HLS experience, data analysis skills, and familiarity with CI workflows. A Master’s or PhD with limited post-grad experience is expected, with a hybrid work arrangement.

Qualifikationen

• Experience in FPGA firmware development using HDL and HLS tools.
• Experience in data analysis, preferably in high-energy physics.
• Practical experience applying machine learning to real-world problems.
• Experience with CI and QA techniques and tools.
• Familiarity with trigger or data acquisition systems and high-speed links.

Aufgaben

• Contribute to development of algorithms for CMS Level-1 trigger.
• Integrate and maintain contributions from other developers.
• Evaluate physics performance and help monitor systems.
• Participate in hardware testing and installation of the upgraded trigger.
• Collaborate with CMS L1 trigger groups at CERN.
• Present progress at meetings and conferences.
• This role includes team supervision responsibilities.

Kenntnisse

C++

Python

Git

Data analysis

Machine learning

CI/QA

Ausbildung

Master's degree (2-6 years post-grad)

PhD (<=3 years post-grad)

Tools

Vivado Design Suite

Vivado/HLS

GitLab

CI workflows

ROOT

ML frameworks

Jobbeschreibung

Join CERN in Geneva as a Developer for the CMS Level-1 Trigger. You will develop FPGA firmware, integrate contributions, and evaluate physics performance for a high-energy physics upgrade. You will test hardware, collaborate with CMS L1 groups, and present results at international conferences.

The role requires FPGA/HLS experience, data analysis skills, and familiarity with CI workflows. A Master’s or PhD with limited post-grad experience is expected, with a hybrid work arrangement.