WIRED IP ASIC DESIGN ENGINEER

Advanced Micro Devices; Ottawa; Hybrid; CAD 90,000 - 130,000; Full time

Job summary

A leading technology company is seeking a talented individual to join its Wired IP Solutions Group as an RTL Design Engineer. In this role, you will work on developing high-performance IP cores for various applications such as networking and security, utilizing your expertise in Verilog and ASIC technology. The position requires strong analytical, problem-solving skills, and the ability to collaborate across multiple teams and time zones. A Bachelor’s or Master's degree in Electrical Engineering is essential for this opportunity.

Benefits

Comprehensive benefits package

Flexible working arrangements

Qualifications

• Expert in Verilog RTL coding and ASIC design.
• Experience with networking protocols and digital communication.
• Familiar with encryption protocols.

Responsibilities

• Develop synthesizable RTL for IP cores targeting advanced technology nodes.
• Collaborate with architecture and verification teams.
• Coach and mentor less experienced designers.

Skills

Verilog RTL coding

Analytical skills

Problem-solving

Communication skills

Education

Bachelor’s or Master's degree in Electrical Engineering

Tools

ASIC design tools

Functional verification tools

Scripting languages (Python, Perl, TCL)

Job description

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

AMD together we advance_

THE ROLE:

We are looking for a talented individual to join our Wired IP Solutions Group (WISG) in an RTL design role. Our intellectual property (IP) design team creates IP cores for use in high performance AMD products. Our designers work on industry-leading technologies for wired communications. Your expertise will be deployed in ASIC projects targeting networking, security, storage, and other applications.

THE PERSON:

You are an expert in Verilog RTL coding, and front-end design flows. You have experience with wired communications protocols, ASIC architecture and design, and EDA design processes. You have demonstrated your technical skill through prior experience delivering ASIC and/or FPGA solutions to the market, and leverage this experience to design and code innovative, high quality IP products.

You are a team player who has excellent written and verbal communication skills with experience collaborating across multiple design sites and time zones. You have strong analytical and problem-solving skills and enjoy tackling new challenges. You are a self-starter with a desire to learn and an ability to solve complex, novel, and non-recurring problems. You pay attention to details. You enjoy working amongst a multi-disciplinary team of professionals with diverse skills and experiences to complete projects in an efficient manner.

KEY RESPONSIBILITIES:

• Develop synthesizable RTL for IP cores targeting advanced technology nodes

• Collaborate directly with IP Architecture, IP Verification, and SoC integration teams

• Contribute to design specifications for IP cores

• Resolve IP simulation regression failures through close collaboration with IP Verification Team and work with Verification Team members to ensure achievement of verification quality metrics

• Work with SoC team and Physical Design (PD) team to meet Power/Performance/Area goals by providing synthesis and timing closure support

• Support the activities of the Emulation Team

• Coach and mentor less experienced designers

• Attend and contribute to regular technical status meetings

PREFERRED EXPERIENCE:

• Significant RTL (Verilog / System Verilog) ASIC design experience through implementations targeting leading edge ASIC technologies

• Proven experience with industry-leading ASIC design tools, synthesis tools, flows, and timing closure

• Experience executing design checks such as lint, CDC, and LEC using industry standard ASIC tools

• Skilled in simulation and debugging with functional verification tools from Synopsys, Cadence, and/or Siemens (Mentor) including Gate-level simulations

• Excellent understanding of standard bus/interface protocols (i.e. AXI, AHB, AMBA)

• Experience in modern, complex networking architecture and digital design in general

• Experience with networking protocols (such as Ethernet) and standards for digital communication systems, optical communications, and packet processing applications

• Familiarity with encryption protocols (such as MACsec and IPsec) and security technologies for digital communication systems

• Proficient with scripting languages such as Python, Perl, TCL, Makefile, and csh/bash

ACADEMIC CREDENTIALS:

• Bachelor’s or Master's degree in Electrical Engineering

LOCATION: Ottawa, Ontario, CA

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.