WIRED IP ASIC DESIGN ENGINEER

AMD; Ottawa; On-site; CAD 85,000 - 125,000; Full time

Job summary

Join a leading technology company as a WIRED IP ASIC DESIGN ENGINEER, where you'll develop high-performance IP cores and collaborate across diverse teams. Candidates should have expertise in Verilog, ASIC design processes, and wired communication protocols. The position offers an opportunity to work on cutting-edge technologies in a collaborative environment.

Benefits

Benefits package

Inclusive workplace

Qualifications

• Experience with wired communication protocols and EDA processes.
• Prior experience delivering ASIC and/or FPGA solutions.
• Ability to tackle novel and complex problems.

Responsibilities

• Develop synthesizable RTL for IP cores targeting advanced technology nodes.
• Collaborate with IP Architecture, IP Verification, and SoC integration teams.
• Coach and mentor less experienced designers.

Skills

Verilog

ASIC design

RTL coding

problem-solving

communication

Education

Bachelor’s or Master's degree in Electrical Engineering

Tools

industry-standard ASIC tools

functional verification tools

scripting languages (Python, Perl, TCL)

Job description

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WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

AMD together we advance_

The Role

We are looking for a talented individual to join our Wired IP Solutions Group (WISG) in an RTL design role. Our intellectual property (IP) design team creates IP cores for use in high performance AMD products. Our designers work on industry-leading technologies for wired communications. Your expertise will be deployed in ASIC projects targeting networking, security, storage, and other applications.

The Person

You are an expert in Verilog RTL coding, and front-end design flows. You have experience with wired communications protocols, ASIC architecture and design, and EDA design processes. You have demonstrated your technical skill through prior experience delivering ASIC and/or FPGA solutions to the market, and leverage this experience to design and code innovative, high quality IP products.

You are a team player who has excellent written and verbal communication skills with experience collaborating across multiple design sites and time zones. You have strong analytical and problem-solving skills and enjoy tackling new challenges. You are a self-starter with a desire to learn and an ability to solve complex, novel, and non-recurring problems. You pay attention to details. You enjoy working amongst a multi-disciplinary team of professionals with diverse skills and experiences to complete projects in an efficient manner.

Key Responsibilities

• Develop synthesizable RTL for IP cores targeting advanced technology nodes
• Collaborate directly with IP Architecture, IP Verification, and SoC integration teams
• Contribute to design specifications for IP cores
• Resolve IP simulation regression failures through close collaboration with IP Verification Team and work with Verification Team members to ensure achievement of verification quality metrics
• Work with SoC team and Physical Design (PD) team to meet Power/Performance/Area goals by providing synthesis and timing closure support
• Support the activities of the Emulation Team
• Coach and mentor less experienced designers
• Attend and contribute to regular technical status meetings
  
  
  

Preferred Experience

• Significant RTL (Verilog / System Verilog) ASIC design experience through implementations targeting leading edge ASIC technologies
• Proven experience with industry-leading ASIC design tools, synthesis tools, flows, and timing closure
• Experience executing design checks such as lint, CDC, and LEC using industry standard ASIC tools
• Skilled in simulation and debugging with functional verification tools from Synopsys, Cadence, and/or Siemens (Mentor) including Gate-level simulations
• Excellent understanding of standard bus/interface protocols (i.e. AXI, AHB, AMBA)
• Experience in modern, complex networking architecture and digital design in general
• Experience with networking protocols (such as Ethernet) and standards for digital communication systems, optical communications, and packet processing applications
• Familiarity with encryption protocols (such as MACsec and IPsec) and security technologies for digital communication systems
• Proficient with scripting languages such as Python, Perl, TCL, Makefile, and csh/bash
  
  
  

Academic Credentials

• Bachelor’s or Master's degree in Electrical Engineering
  
  
  

LOCATION: Ottawa, Ontario, CA

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Industries

  Semiconductor Manufacturing

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