Staff ASIC Design Engineer

HRB; Canada; Remote; CAD 100,000 - 160,000; Full time

Job summary

A leading company in Canada seeks a Staff ASIC Design Engineer to contribute to a team developing IP for ASICs and FPGAs. The ideal candidate will leverage extensive experience in design methodologies and contribute creatively to complex engineering challenges. Success in this role requires a strong willingness to collaborate, communicate, and lead in a fast-paced environment.

Qualifications

• 10+ years of experience in ASIC design.
• Strong knowledge with RTL programming languages.
• Track record of successful tape outs in advanced process nodes.

Responsibilities

• Apply industry best practices in ASIC development.
• Design and code RTL modules.
• Perform hardware testing and verification.

Skills

Communication

Creative Thinking

Critical Thinking

Problem Solving

Education

B.S, M.S, or Ph.D in Electrical Engineering

Computer Engineering

Computer Science

Tools

Verilog/SystemVerilog

TCL

Python

Job description

We are looking for aStaff ASIC Design Engineerto contribute to a team developing IP for both ASICs and FPGAs. The ideal candidate is a strong communicator, creative, a critical thinker, and able to analyze and resolve complex issues.

Responsibilities

• • Apply industry best practices in ASIC development to achieve best in class designs
  • Design, propose, and oversee the analysis/evaluation of hardware architectures
  • Design and code RTL modules written in Verilog/SystemVerilog
  • Simulate and perform hardware-based testing, debug, and verification
  • Scripting and basic software development in support of hardware design
  • Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment

Requirements

• • B.S, M.S, or Ph.D in Electrical Engineering, Computer Engineering or Computer Science
  • Track record of successful tape outs in advanced process nodes
  • 10+ years of experience in ASIC design
  • Experience in ASIC design methodologies, including code quality checking, synthesis, physical design, and power estimation design tools
  • Strong knowledge with RTL programming languages Verilog/SystemVerilog (preferred), or VHDL
  • Ability to read and write code in TCL/Python (C, C++ are assets)

Preferred Skills & Experience

• • Deep experience with ASIC or FPGA timing closure and physical design
  • Working experience with AMBA protocols, PCIe, UCIe, and HBM will be an asset
  • Experience with Agile development methodologies
  • Experience in technical leadership of small teams