Senior Wireless Digital Verification Engineer

Qualcomm; Vancouver; On-site; CAD 80,000 - 130,000; Full time

Job summary

Qualcomm is seeking a Hardware Engineer to join their dynamic ASIC Engineering team in Vancouver. This role focuses on the design verification of advanced SoCs, emphasizing wireless technologies. Candidates should have a solid background in digital design and verification, and be skilled in modern methodologies like SystemVerilog. If you're ready to contribute to cutting-edge technology in a collaborative environment, this is the opportunity for you.

Qualifications

• 2-15 years of experience in digital design and verification.
• Deep understanding of bus protocols and bridge logic.
• Experience with power-aware verification methodologies and tools.

Responsibilities

• Develop and execute verification plans for complex SoC designs.
• Architect and implement testbenches using SystemVerilog.
• Collaborate with cross-functional teams to ensure functional correctness.

Skills

Analytical skills

Debugging

Communication

Education

Bachelor's degree in Computer Science

Master's degree in Electrical/Electronics Engineering

PhD in Electrical/Electronics Engineering

Tools

SystemVerilog

UVM/OVM

Perl

Tcl

Python

Job description

Company:

Qualcomm Canada ULC

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

General Summary:

Join Qualcomm’s cutting-edge hardware engineering team to drive the design verification of next-generation SoCs, with a focus on wireless technologies including WLAN (IEEE 802.11). You will work on IP and subsystem-level verification, collaborating with cross-functional teams to deliver high-performance, low-power silicon solutions. A strong understanding of on-chip buses and bridges is essential to ensure seamless integration and performance across subsystems.

Key Responsibilities:

Develop and execute verification plans for complex SoC designs and IP blocks.

Architect and implement testbenches using SystemVerilog and UVM/OVM methodologies.

Perform RTL verification, simulation, and debugging.

Collaborate with design, architecture, and software teams to ensure functional correctness.

Contribute to IP design reviews and sign-off processes.

Support post-silicon validation and bring-up activities.

Analyze and verify interconnects, buses (e.g., AMBA AXI/AHB/APB), and bridges for performance and protocol compliance.

Conduct CPU subsystem verification including coherency, cache behavior, and interrupt handling.

Perform power-aware verification using UPF/CPF and validate low-power design intent.

Execute performance verification to ensure bandwidth, latency, and throughput targets are met

Preferred Skills & Experience:

2–15 years of experience in digital design and verification.

Deep understanding of bus protocols and bridge logic, including hands-on experience with AXI, AHB, and APB.

Experience with CPU subsystem verification and performance modeling.

Familiarity with wireless protocols (IEEE 802.11 a/b/g/n/ac/ax/be) is a plus.

Proficiency in SystemVerilog, UVM/OVM, Verilog, and scripting languages (Perl, Tcl, Python).

Experience with power-aware verification methodologies and tools (e.g., UPF, CPF).

Familiarity withperformance verification techniques and metrics.

Exposure to tools like Clearcase/Perforce and simulation/debug environments.

Strong analytical, debugging, and communication skills.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.

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