Senior Staff Analog Circuit Design Engineer - SerDes

Intel; Toronto; Hybrid; CAD 182,580 - 257,760; Full time

Job summary

Intel is seeking a Senior Staff Analog Circuit Design Engineer to validate cutting-edge SerDes technologies. You will work with diverse teams on validation challenges, enhancing product quality and innovation.

This role, located in the Toronto area, currently offers remote work. Ideal candidates will hold a degree in Electrical Engineering and have significant experience in SerDes validation.

Qualifications

• 3+ years of relevant experience in post-silicon validation.
• 2+ years of experience in SerDes validation and debugging.
• Experience with mixed-signal testing strategies.

Responsibilities

• Design and implement validation plans for SerDes IP.
• Conduct root cause analysis on design failures.
• Generate detailed validation reports.

Skills

Analytical and problem-solving capabilities

Collaboration and communication skills

Programming experience with Python, C, C++

Education

Bachelor’s degree in Electrical Engineering or related discipline

Job description

Role Overview And Impact

Join Intel as a Senior Staff Analog Circuit Design Engineer – SerDes and become instrumental in validating our industry‑leading SerDes technologies. In this critical role, you’ll ensure our mixed‑signal designs meet the highest standards for reliability, functionality, and performance. Your technical expertise will directly influence product quality and strengthen Intel’s competitive edge in the semiconductor market. Working alongside diverse engineering teams, you’ll tackle sophisticated validation challenges, drive technological innovation, and shape the development of next‑generation hardware platforms. This position offers an exceptional opportunity to create meaningful impact within Intel’s dynamic engineering organization while contributing to the future of technology.

Core Responsibilities

• Design, develop, and implement comprehensive functional validation plans for industry‑leading SerDes IP.
• Create and enhance validation frameworks while partnering with cross‑functional teams on design optimization, troubleshooting, and failure resolution.
• Conduct thorough root cause analysis and systematic debugging of mixed‑signal design failures and functional issues.
• Build and maintain post‑silicon validation workflows and status reports.
• Generate detailed validation reports documenting testing activities, outcomes, and improvement recommendations.
• Partner with architecture, design, verification, board, platform, and manufacturing teams to optimize debugging processes and validation methodologies for mixed‑signal interfaces.

Core Competencies

• Exceptional analytical and problem‑solving capabilities for complex technical challenges.
• Outstanding collaboration and communication skills for effective cross‑functional teamwork.
• Passion for innovation combined with unwavering commitment to quality excellence.

Qualifications

Special Note

- Intel is in the process of securing office space in the greater metropolitan area of Toronto, Ontario. This office will serve as your assigned work location in the future. Once the site is operational, your position will follow Intel’s hybrid work model, which currently requires on‑site presence at least four days per week. Until the office is ready, you will be classified as a remote employee and will be working virtually from the greater metropolitan area of Toronto, Ontario.

Minimum Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related technical discipline and 3+ years of relevant experience.
• 2+ years of experience in SerDes post‑silicon validation and debug processes.
• Experience in I/O principles and mixed‑signal testing approaches.
• Experience in test planning, validation strategy formulation, and post‑silicon validation workflows.

Preferred Qualifications

• Post‑graduate degree in Electrical Engineering, Computer Engineering, or related technical discipline.
• Experience with electrical validation and debugging of 224G+ SerDes IP.
• Experience developing validation infrastructure and specialized testing tools.
• Programming experience with Python, C, C++.

Job Type

Experienced Hire

Shift

Shift 1 (Canada)

Primary Location

Virtual Canada

Business Group

The Central Engineering Group (CEG) is Intel’s data‑driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer‑driven, end‑to‑end solutions with short development cycles to deliver measurable business impact across Intel’s product and foundry businesses.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Annual Salary Range for jobs which could be performed in Canada

CAD 182,580.00 – 257,760.00

Work Model for this Role

This role is available as a fully home‑based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. Job posting details (such as work model, location or time type) are subject to change.

Canada Accommodation

Intel is committed to a culture of accessibility. Intel provides accommodations to applicants and employees with disabilities. Find information and request accommodation here.

Additional Information

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.