Senior DSP Firmware Engineer

Celero Communications; Ottawa; On-site; CAD 150,000 - 250,000; Full time

Job summary

Celero Communications in Ottawa is seeking a Senior DSP Firmware Engineer to design and debug firmware for advanced DSP algorithms on next-generation silicon platforms. The role involves close collaboration with architects and designers to enhance firmware performance and mentor junior engineers.

Successful candidates will have a strong background in DSP fundamentals, C/C++ programming, and firmware development, as well as a degree in a relevant field. The compensation ranges from $150,000 to $250,000 annually.

Qualifications

• 3–5 years of relevant experience in embedded/firmware development.
• Strong hands-on expertise in programming and firmware development.
• Ability to work cross-functionally with systems and hardware teams.

Responsibilities

• Design, implement, and maintain firmware for DSP algorithms.
• Optimize firmware for real-time operation and resource usage.
• Mentor and guide junior firmware engineers.

Skills

Digital Signal Processing (DSP)

C/C++ programming

Firmware development for DSP systems

Debugging tools

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

FFT algorithms

Lab tools (JTAG debuggers, oscilloscopes)

Job description

Senior DSP Firmware Engineer

We are seeking a Senior DSP Firmware Engineer to design, implement, and debug firmware supporting advanced DSP algorithms on next‑generation silicon platforms. You will work closely with system architects, DSP designers, and verification teams to deliver high‑performance firmware across pre‑silicon and post‑silicon environments. This role is ideal for a hands‑on engineer with strong DSP fundamentals who can accelerate development, own defined subsystems, and contribute to mentoring junior engineers.

Locations

Irvine, Ottawa Ontario, Argentina

Key Responsibilities

• Design, implement, and maintain firmware supporting advanced DSP algorithms on embedded processors.
• Design finite state machines governing DSP acquisition and tracking control loops.
• Optimize firmware for real‑time operation, latency, throughput, and resource usage to meet firmware specifications.
• Own pre‑silicon test‑driven development framework for DSP firmware.
• Generate and integrate Hardware Abstraction Layer with simulation and emulation platforms.
• Collaborate with verification teams to align firmware validation strategy with regression infrastructure.
• Debug complex firmware, DSP, and system‑level issues.
• Analyze issues using firmware logs, traces, and instrumentation.
• Support regression testing teams by identifying root causes and improving test coverage.
• Enforce firmware coding standards, test coverage and best practices.
• Mentor and guide junior firmware engineers.
• Contribute to defining development workflows and long‑term maintainability.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 3–5 years of relevant experience in embedded/firmware development.
• Strong background in Digital Signal Processing (DSP) fundamentals and algorithm implementation.
• Experience optimizing FFT algorithms and FFT‑based resampling (preferably on SiFive processors).
• Strong hands‑on expertise in:
  • Programming: C/C++
  • Firmware development: for DSP‑centric embedded systems
  • Debug and analysis tools: tracing, profiling, logging, and hardware/software debuggability
• Ability to work cross‑functionally with systems, DSP, verification, and hardware teams.
• Strong communication skills and ability to mentor junior engineers.

Preferred Qualifications

• Experience working in coherent optical systems, silicon photonics.
• Knowledge of RISC V architecture (SiFive or similar).
• Familiarity with:
  • FPGA and emulation platforms for pre silicon validation
  • Lab bring up tools, including JTAG debuggers, logic analyzers, and oscilloscopes
  • UVM based verification environments and SystemVerilog test methodologies

Compensation

$150,000 – $250,000 Base Annually. The final offer will be determined based on job‑related skills, experience, qualifications, and location.