Senior Digital Design Engineer

Eliyan Corporation; Vancouver; On-site; CAD 90,000 - 150,000; Full time

Job summary

An innovative startup at the forefront of chiplet technology is seeking a Senior Digital Designer to join their dynamic team. In this role, you will develop cutting-edge micro-architecture specifications and RTL designs for high-performance Ethernet systems. With a focus on power, area, and manufacturability, you will collaborate with experts to push the boundaries of digital design. This position offers a vibrant work environment filled with opportunities for creativity and innovation, making it ideal for those passionate about shaping the future of technology.

Benefits

Excellent benefits

Fun work environment

Qualifications

• 8+ years of experience in high-speed digital design, especially in Ethernet PMA/PCS.
• Strong expertise in RTL and Assertion coding with SystemVerilog.

Responsibilities

• Design and develop Ethernet PCS/PMA IPs for various data rates.
• Collaborate with verification engineers for IP verification.

Skills

SystemVerilog

RTL Design

Ethernet Standards (IEEE 802.3)

High-speed Digital Design

Power Optimization

Digital Design Automation

Education

Bachelor in Electrical Engineering

Master in Electrical Engineering

Ph.D. in Electrical Engineering

Job description

Join the leading chiplet startup! As an Eliyan senior digital designer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will be developing micro-architecture specifications and RTL design descriptions for best-in-class PHYs and Controllers. You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits.

Key Responsibilities

• Design, develop and/or integrate Ethernet PCS/PMA IPs for various data rates (100/200/400/800G)
• Develop micro-architecture specifications and implement digital designs using SystemVerilog
• Ensure compliance with Ethernet standards (IEEE 802.3)
• Optimize designs for power, area, and performance
• Collaborate with verification engineers for IP verification
• Work closely with physical design team for physical implementation
• Participate in design reviews and ensure design quality
• Develop and maintain all IP design collaterals that include documentation, RTL, SDC constraints, powerintent definition (UPF/CPF), LINT/CDC rule files and waivers
• Stay up to date with industry trends, emerging technologies and progress in standards’ bodies

Qualifications

• Bachelors or Masters or Ph.D in Electrical Engineering and related fields, or equivalent
• 8+ years of experience in high-speed digital design (preferably in retimer, gearbox, Ethernet PMA/PCSlogic)
• Strong expertise in RTL and Assertion coding with SystemVerilog
• Proficiency in taking RTL through synthesis and produce a PPA optimized frontend netlist
• Knowledge of Ethernet 802.3 standards’ clauses related to 100G/200G/400G/800G, Auto-Negotiationand Link Training
• Strong bias for innovations across all aspects of digital design including automation of mundaneactivities and methods for quality improvement
• Experience integrating 3rd party mixed signal IPs
• Proven track record of being part of a start-up like environment
• Expertise in Forward Error Correction (FEC) code implementation and performance analysis
• Knowledge of DRAM Controllers/PHYs and HBM Memory a plus