Senior ASIC Verification Engineer

European Tech Recruit; Ottawa; On-site; CAD 100,000 - 130,000; Full time

Job summary

A Semiconductor design company is seeking a Senior ASIC Verification Engineer to join their team. This role involves ensuring the functional integrity of complex System-on-Chips (SOCs) and leveraging expertise in SystemVerilog and UVM for advanced ASIC projects. The ideal candidate will have at least eight years of experience and a strong track record in ASIC verification.

Qualifications

• Minimum of eight years of ASIC verification experience.
• Proficiency in Verilog, SystemVerilog, and other hardware description languages.

Responsibilities

• Work on verification for assigned blocks or entire chips.
• Design scalable and robust verification environment architecture.
• Document test environment associations and create comprehensive test cases.

Skills

SystemVerilog

UVM

Scripting languages

Verification Techniques

Tools

Verilog

Job description

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A Semiconductor design company is looking for an experienced ASIC Verification Engineer to join their team, working on a variety of cutting-edge projects across various products in the Semiconductor space.

Due to stable and organic growth, supported by a strong industry reputation, the business is expanding and aims to enhance their current design expertise.

Overview:

Join our team as a Senior ASIC Verification Engineer and contribute to the success of advanced ASIC projects at technology nodes down to 3nm FinFET. As a key member of our highly skilled team, you will play a pivotal role in ensuring the functional integrity of complex System-on-Chips (SOCs). Leverage your expertise in SystemVerilog, UVM, and scripting languages to drive verification activities using state-of-the-art methodologies and tools.

Key Responsibilities:

• Verification Activities: Work on verification for assigned blocks or entire chips, ensuring adherence to project timelines. Develop robust verification environments using SystemVerilog, UVM, and scripting languages.
• Verification Environment Architecture: Design scalable and robust verification environment architecture with UVM.
• Test Case Development: Document test environment associations, create comprehensive test cases, and apply constrained random verification techniques to enhance coverage. Support lab bring-up, execute test cases, and troubleshoot as needed.
• Analysis: Perform code and functional coverage analysis to ensure comprehensive verification.

Key Qualifications:

• Minimum of eight years of ASIC verification experience with a successful project track record.
• Proficiency in Verilog, SystemVerilog, and other hardware description languages.
• Expertise in scripting languages.
• Deep understanding of OVM/UVM methodologies and advanced verification techniques.
• Familiarity with constrained random verification, assertions, and functional coverage.

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Seniority level

• Mid-Senior level

Employment type

• Full-time

Job function

• Engineering and Information Technology

Industries

• Staffing and Recruiting