R&D Engineering, Sr Staff Engineer - Design Verification/ VIP Verification Engineers

Synopsys, Inc.; Mississauga; On-site; CAD 80,000 - 120,000; Full time

Job summary

An established industry player is seeking a passionate R&D Engineer to drive innovations in system verification. This role involves architecting and building cutting-edge verification solutions for high-performance computing, automotive systems, and IoT applications. You will collaborate with market leaders to ensure the integrity of verification protocols while enhancing product quality through rigorous verification processes. If you are a team player with strong analytical skills and a creative mindset, this is an exciting opportunity to contribute to technological advancements and make a significant impact in the industry.

Qualifications

• 8-12 years of experience in system verification or 6-10 years with a Master's degree.
• Hands-on experience with SystemVerilog UVM-based verification components.

Responsibilities

• Functional verification of coherent and non-coherent IP designs.
• Collaborating with leaders in High Performance Computing and Automotive sectors.

Skills

SystemVerilog

UVM

Perl

Python

Shell Scripting

Problem-Solving

Analytical Skills

Education

B.E/B.Tech in Electrical Engineering

M.E/M.Tech in VLSI Design

Tools

Verification IPs

Testbenches

Scoreboards

Job description

We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:
You are a passionate and skilled R&D Engineer with a deep understanding of system verification. You are enthusiastic about developing cutting-edge verification solutions for high-performance computing, data centers, mobile/client devices, automotive systems, and IoT segments. Your experience in architecting and building SystemVerilog UVM-based verification components, coupled with your expertise in cache coherency protocols and functional verification, makes you an ideal candidate for this role. You are a team player with excellent problem-solving abilities, strong analytical skills, and a keen attention to detail. Your background in verification IP development and your programming prowess in languages like Perl, Python, and Shell scripting set you apart as a valuable asset to our team.

What You’ll Be Doing:
* Responsible for functional verification involving coherent and non-coherent IP designs.
* Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements.
* Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs.
* Developing verification plans and driving functional coverage-driven verification closure of real designs.
* Debugging and resolving issues in verification environments to ensure robust and reliable verification processes.

The Impact You Will Have:

* Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes.
* Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols.
* Driving innovation in the automotive sector by developing robust verification solutions for automotive systems.
* Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices.
* Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements.
* Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products.

What You’ll Need:
* B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 8-12 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 6-10 years of relevant experience.
* Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs.
* You will be responsible for functional verification involving coherent and non-coherent IP designs.

Protocol experience: Should have experience on UCIe/PCIe/CXL/Unipro/USB/MIPI/HDMI/Ethernet/DDR/LPDDR/HBM memory protocol

Who You Are:
* Excellent problem-solving, debugging, and analytical skills.
* Strong programming skills and familiarity with object-oriented programming concepts.
* Creative and innovative mindset.
* Excellent verbal and written communication skills.
* A collaborative team player with a passion for functional verification.