Principal Design Engineer

Cadence Design Systems; Eastern Ontario; On-site; CAD 100,000 - 125,000; Full time

Job summary

An established industry player is seeking a skilled digital design engineer to join their innovative team focused on High Speed SerDes. This role offers the opportunity to work on cutting-edge technology, requiring a deep understanding of digital design flows and collaboration with both analog and digital teams. The ideal candidate will bring over five years of experience, a Master's degree in Electrical Engineering, and a passion for solving complex challenges in technology. Join a forward-thinking company where your contributions will drive impactful advancements in the field and help shape the future of digital design.

Qualifications

• 5+ years of digital design experience with a focus on SerDes.
• Hands-on experience with digital designs in FPGAs or ICs.

Responsibilities

• Define and document digital microarchitecture for projects.
• Collaborate with technical staff on project development progress.

Skills

SerDes

Digital microarchitecture

RTL logic design

Digital architecture trade-offs

Static timing analysis

DSP and algorithms

Education

Master’s degree in Electrical Engineering

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This team is focused on High Speed Serdes. The ideal candidate will have at least 5 plus years of actual work experience in SerDes as well as a thorough understanding of the end-to-end digital design flow to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status. This includes but is not limited to:

1. Digital microarchitecture definition and documentation
2. RTL logic design, debug and functional verification
3. Understanding of digital architecture trade-offs for power, performance, and area
4. Understanding of proper handling of multiple asynchronous clock domains and their crossings
5. Understanding of Lint checks, UPF checks and proper resolution of errors
6. Understanding synthesis timing constraints, static timing analysis and constraint development
7. Understanding of fundamental physical design flows and stages
8. Understanding of wireline standards and collaborating with standards experts to relate standard requirements to logic specifications
9. Experience on silicon bring-up and testing of wireline IP
10. Strong background in DSP and algorithms is a plus

Requested Skill Set

1. Master’s degree or higher in Electrical Engineering
2. Minimum 5 years of digital design work experience
3. Hands-on experience in implementing and demonstrating digital designs in FPGAs or ICs

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We welcome applications from candidates with disabilities and in equity seeking groups. If you have accessibility needs during the application and interview process, we encourage you to make your needs known.