Logic Design Engineer

NXP Semiconductors NV; Ottawa; Sur place; CAD 72 000 - 99 000; Plein temps

Avantages offerts par ce poste

Health, dental, vision

RRSP

Equity (certain roles)

Résumé du poste

NXP Semiconductors in Ottawa, Canada, is seeking an experienced engineer to architect, design and implement Ethernet/IP for next-generation automotive, industrial and edge computing SoCs.

You will handle micro-architecture, Verilog RTL implementation, logic synthesis and timing closure, while collaborating with IP design verification and front-end teams to ensure timely, high-quality IP delivery.

Qualifications

• Experience in RTL design of complex digital IP is desirable.
• Knowledge in Verilog RTL design, logic synthesis, coverage analysis and timing closure.
• Understanding IP development methodology and proficiency in front-end design tools.
• Knowledge of state-of-the-art networking technologies including TCP/IP protocols is desirable.
• Experience with data products such as routers, bridges and switches is desirable.
• Security/cryptography experience would be an asset.
• Strong architecture and design skills are desirable but not required.
• Should be familiar with hardware and software implementation trade-offs.
• Ability to solve system wide problems.
• Algorithm development experience is desirable but not required.
• Must work well in a team environment.

Responsabilités

• Architect, design and implement breakthrough Ethernet/networking IP to be integrated into next-generation SoCs for automotive, industrial and edge computing markets.
• Responsible for micro-architecture, Verilog RTL implementation, logic synthesis and timing closure.
• Perform trade-off analysis on performance/area/complexity.
• Ensure front-end to back-end handoff IP quality checks such as Lint/CDC/Synthesis/STA/LEC and other.
• Provide technical support to our engineering IP team, including code reviews, and assist in project planning and tracking.
• Working closely with IP design verification engineers on planning and execution, to ensure the IP is delivered on time and with highest quality.
• Quality documentation for all phases of the project; e.g. quality detailed IP functional and implementation specifications.
• Proactively drive continuous improvement in design methodology.

Connaissances

Verilog RTL design

RTL design of complex IP

Logic synthesis

Timing closure

Team collaboration

Formation

Bachelor's degree in Computer Science, Engineering or related field

Outils

Front-end design tools

Description du poste

Business Line Description

Be an integral member of a highly-experienced team in R&D that is responsible for developing IP (Intellectual Property) used in the design of advanced microcontrollers and microprocessors. The IP for which this team is responsible enables a product portfolio with billion USD in annual revenue. Chances are that the car you drive, the intelligent devices that pervade your living space and the factories that produce the goods you use will contain one or more of the chips that you contribute to. The IP itself is challenging and of significant scope as it requires implementing very complicated and challenging algorithms in hardware/silicon. It incorporates latest Ethernet technology such as IEEE Time Sensitive Networking (TSN) that extends Ethernet for safety-critical and real-time applications.

We are part of Advanced Chip Engineering, a central design organization within NXP, developing products for multiple business lines in Automotive, Internet of Things (IoT), Networking, and Radio Frequency products, with expertise in hardware engineering, including architecture, IP, and full SoC Design.

Job Summary

• Architect, design and implement breakthrough Ethernet/networking IP to be integrated into next-generation SoCs for automotive, industrial and edge computing markets.
• Responsible for micro-architecture, Verilog RTL implementation, logic synthesis and timing closure.
• Perform trade-off analysis on performance/area/complexity.
• Ensure front-end to back-end handoff IP quality checks such as Lint/CDC/Synthesis/STA/LEC and other.
• Provide technical support to our engineering IP team, including code reviews, and assist in project planning and tracking.
• Working closely with IP design verification engineers on planning and execution, to ensure the IP is delivered on time and with highest quality.
• Quality documentation for all phases of the project; e.g. quality detailed IP functional and implementation specifications.
• Proactively drive continuous improvement in design methodology.

Key Challenges

• The IP itself is challenging and of significant scope as it requires implementing very complicated and challenging algorithms in hardware/silicon. It incorporates latest Ethernet technology such as IEEE Time Sensitive Networking (TSN) that extends Ethernet for safety-critical and real-time applications.
• IP requires a well-thought-out scalable micro-architecture and proper parameterization that enables to grow the area/power linearly as the performance, capacity and functionality required, need to be increased.
• IP developed in the team needs to be of high quality and implementation ready, requiring strong interactions with the SoC integration and implementation teams

Cross functional aspects

• Interaction with architecture, software and marketing for IP definition and roadmap
• Work closely with SoC front-end integration and implementation, for IP execution.
• Interaction with the application engineering to resolve customer issues.

Job Qualifications

• Some experience in RTL design of complex digital IP is desireable but not required
• Knowledge in Verilog RTL design, logic synthesis, coverage analysis and timing closure
• Understanding of IP development methodology and proficiency in front-end design tools
• Knowledge of state-of-the-art networking technologies including TCP/IP protocols is desirable but not required
• Experience with data products such as routers, bridges and switches is desirable.
• Security/cryptography experience would be an asset
• Strong architecture and design skills are desirable but not required
• Should be familiar with hardware and software implementation trade-offs.
• Ability to solve system wide problems.
• Algorithm development experience is desirable but not required
• Must work well in a team environment.
• Strong interpersonal, communication, and documentation skills.
• Bachelors in Computer Science, Engineering or related education required

Job location

Ottawa, Canada

Base Salary

The base salary range for this position is as mentioned below per year. Please note that the base salary range (OR hourly rate) is a guideline, and individual total compensation may vary based on a number of factors such as qualifications, skill level, work location, and other business and organizational needs. This base pay range is specific to Canada and is not applicable to other locations. A reasonable estimate of the base salary range as of the date of this posting is from $72,000 to $99,000 CAD per year.

Benefits

• We offer health, dental, vision, wellness, saving programs and RRSP.
• We also provide competitive benefits, incentive compensation, and/or equity for certain roles.

More information about NXP in Canada...