Graduate Design Engineer

Arm; Toronto; Hybrid; CAD 67,600 - 91,400; Full time

Benefits offered by this job

Competitive salary

Comprehensive rewards package

Graduate-level events and workshops

Job summary

A leading semiconductor company is seeking an RSE Design Engineer to contribute to the development of secure subsystem architectures. This role involves collaborating with design teams, improving automation workflows, and maintaining package dependencies across subsystems. Ideal candidates hold a relevant degree and possess skills in RTL design, scripting, and version control. The position offers a competitive salary and opportunities for career growth within a hybrid work environment.

Qualifications

• Hold a relevant degree or have equivalent experience.
• Familiarity with synthesis, timing, and DFT concepts.
• Internship or project experience in semiconductor or system-design environments.

Responsibilities

• Contribute to the design and integration of RSE components.
• Maintain package dependencies across RSE subsystems.
• Support BoM release flows and assist with architecture within RSE.

Skills

Knowledge of RTL design with Verilog/SystemVerilog

Experience scripting in Python, Shell, or Tcl

Familiarity with version control systems

Education

Bachelor, Master, or PhD in Computer Engineering or Electrical Engineering

Tools

EDA tools

IP-XACT

Job description

Job Overview

Arm’s Security Technology Team is seeking an RSE (Runtime Security Engine) Design Engineer to support the development of secure subsystem architectures, RTL design, and automation flows. This role offers the opportunity to learn from experienced engineers and contribute to Arm’s next-generation secure computing platforms.

What You Could Be Doing

You will work with design and architecture teams to support the creation, integration, and delivery of the RSE subsystem.

• Contribute to the design and integration of RSE components and review IP for quality and integration readiness.
• Maintain package dependencies across RSE and related subsystems to ensure structural integrity and reduce redundancy.
• Support BoM release flows and assist with clock, reset, and DFT architecture within the RSE subsystem.
• Improve automation and design flows—including IP-XACT and register generation—and collaborate with cross-functional teams through functional and structural sign-off.

We are looking for individuals who

Hold (or are on track to hold) a Bachelor, Master, or PhD in Computer Engineering, Electrical Engineering, or another relevant major. Candidates with alternative degrees will also be considered if they have relevant experience.

Qualities That Will Help Your Application Stand Out

• Knowledge of RTL design with Verilog/SystemVerilog and familiarity with synthesis, timing, and DFT concepts.
• Experience scripting in Python, Shell, or Tcl, with exposure to EDA tools and automation workflows.
• Familiarity with version control systems and SoC integration tools such as IP-XACT or register-generation frameworks.
• Internship, co-op, or project experience in semiconductor, hardware, or system-design environments.

In Return

In addition to a competitive salary and comprehensive rewards package, you’ll also receive support, autonomy, and opportunities to excel in your career. You’ll have two performance review windows each year and access to graduate-level events, workshops, and a global graduate conference.

Salary Range

$67,600-$91,400 per year

Accommodations at Arm

We want to build extraordinary teams. If you need an accommodation during the recruitment process, please email [e-mail]. All accommodation or adjustment requests will be treated with confidentiality and are disclosed only as necessary.

Hybrid Working at Arm

Arm’s approach to hybrid working supports both high performance and personal wellbeing. We empower teams to determine their own hybrid patterns within local legal and regulatory constraints.

Equal Opportunities at Arm

Arm is an equal‑opportunity employer committed to a diverse, inclusive workplace and non‑discrimination across all protected characteristics.