Design Architect Analog IC Designer

Cadence; Toronto; On-site; CAD 120,000 - 180,000; Full time

Job summary

Cadence seeks a senior Design Architect Analog IC Designer in Toronto to lead analog/mixed-signal block design from concept through verification and contribute to long-reach SerDes projects.

The role requires extensive SerDes/SSO experience, strong problem-solving, and teamwork to drive designs via CAD tools, lab testing, and final tape-out readiness.

Qualifications

• Minimum 10 years in CMOS SerDes or high-speed I/O IC development.
• Deep understanding of jitter and signal equalization techniques.
• Proficiency with CAD tools for circuit simulation and post-layout verification.
• Experience with Cadence, lab tests, and ≥16Gbps designs in ≤16nm tech.
• M.S. or Ph.D. in Electrical Engineering.

Responsibilities

• Design and develop analog/mixed-signal IC blocks from concept to verification.
• Contribute to long-reach SerDes circuit design across blocks (TX, RX, PLL, etc.).
• Collaborate across teams; communicate findings and solutions effectively.
• Utilize CAD tools for simulation and verification; assist layout as needed.

Skills

SerDes blocks

CMOS SerDes

High-speed I/O

Jitter control

Signal equalization

Driver

Receiver

Serializer

Deserializer

Phase Interpolator

PLL

Clock distribution

ADC

DAC

Bandgap

Voltage regulators

Cadence tools

Layout knowledge

Lab testing

16Gbps experience

≤16nm technology

Education

MS in EE

PhD in EE

Tools

Cadence tools

Circuit simulation

Post-layout verification

Layout entry

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This role is for an existing vacancy.

Job Description

The Design Architect Analog IC Designer is responsible for the design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications. The Design Architect Analog IC Designer contributes to the design of long-reach SerDes.

• Candidate’s background should include a minimum of 10 years of experience in the development of CMOS SerDes or high-speed I/O IC
• Must have a thorough understanding of jitter and signal equalization techniques
• Proficient design experience in most of the following SerDes circuit blocks: Driver; Receiver; Serializer; Deserializer; Phase Interpolator; Low jitter PLL; High Speed Clock Distribution; ADC and DAC; Bias and Bandgap; and Voltage Regulators
• Excellent problem-solving skills, good communication skills, and ability to work cooperatively in a team environment
• Working knowledge of a set of common SerDes standards and their electrical requirements is a plus
• Position requires proficiency in using CAD tools for circuit simulation, and post-layout verification. Proficiency with layout entry a plus
• Cadence tool experience, lab test experience, and design experience at ≥16Gbps and in ≤16nm technologies
• MS or PhD in EE

Description De L’Emploi

L’Architecte en Conception de Circuits Intégrés Analogiques est responsable de la conception et du développement de circuits analogiques/mixtes, de l'architecture et de la spécification initiale jusqu'à la vérification finale de la conformité aux spécifications du client. L’Architecte en Conception contribue à la conception de SerDes (Serialiseur/Deserialiseur) de longue portée.

• Le candidat doit avoir au minimum 10 ans d'expérience dans le développement de circuits intégrés CMOS SerDes.
• Doit avoir une compréhension approfondie du jitter et des techniques d'égalisation du signal.
• Expérience dans la conception de la plupart des blocs de circuits SerDes : TX, RX, sérialiseur, désérialiseur, interpolateur de phase, PLL, distribution d’horloge à haute vitesse, ADC et DAC, circuits de polarisation et de référence de tension (Bandgap), et régulateurs de tension.
• Excellentes compétences en résolution de problèmes, bonnes capacités de communication et aptitude à travailler en équipe.
• Une connaissance pratique d’un ensemble de normes SerDes courantes et de leurs exigences électriques est un atout.
• Le poste nécessite la maîtrise des outils CAD pour la simulation de circuits et la vérification post-layout. La maîtrise de layout est un plus.
• Une expérience avec les outils Cadence, les tests en laboratoire, ainsi que la conception à des vitesses ≥16 Gbps et dans des technologies ≤16 nm.
• Diplôme de M.Sc ou Ph.D. en génie électrique.

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