ASIC/RTL Design Engineer 5 # 26-27793

US Tech Solutions; Markham; Presencial; CAD 120.000 - 160.000; Jornada completa

Descripción de la vacante

US Tech Solutions is seeking a skilled low-power design engineer in Canada to drive power strategies for complex SoC/IP designs, focusing on synthesis, timing closure, and PPA optimization.

You will collaborate with RTL, physical design, and verification teams across time zones, employing industry-standard tools to ensure efficient, reliable silicon that meets product requirements. A detail-oriented, collaborative mindset is essential.

Formación

• Strong background in ASIC synthesis and static timing analysis (STA).
• Hands-on expertise with EDA tools such as Synopsys Design Compiler, PrimeTime, PrimePower, Power Artists, or equivalent.
• Experience with power analysis and optimization techniques (clock gating, multi-Vt, power gating, multi-voltage design).
• Familiarity with UPF/CPF power intent specification and verification.
• Solid understanding of digital design fundamentals, RTL coding (Verilog/SystemVerilog).
• Experience with advanced process nodes (e.g., 7nm, 5nm, 3nm) is a strong plus.
• Proficiency in scripting languages (TCL, Perl, Python, or Shell) for flow automation.
• Exposure to floorplanning, place-and-route, and ECO flows is desirable.
• Knowledge of low-power design methodologies and trade-offs.
• Prior leadership, mentorship, or cross-functional collaboration experience is an asset.
• Experienced with Verilog, System Verilog, C, and C++
• Graphics pipeline knowledge
• Automating workflows in a distributed compute environment.

Responsabilidades

• Develop and implement power reduction strategies across SoC/IP design.
• Perform synthesis and static timing analysis (STA) to achieve PPA targets.
• Analyze and optimize dynamic and leakage power using industry-standard tools.
• Work closely with RTL designers, physical design, and verification teams to ensure timing and power requirements are met.
• Run low-power verification checks (UPF/CPF) and validate correct power intent implementation.
• Support sign-off activities for Lint , CDC , synthesis, timing, and power closure.
• Automate and streamline power and timing workflows to improve efficiency.
• Build test plan documentation, accounting for interactions with other features, the hardware.

Conocimientos

ASIC synthesis

STA

Verilog/SystemVerilog

Scripting TCL/Python

Power optimization

Herramientas

Synopsys Design Compiler

PrimeTime

PrimePower

PowerArtists

Descripción del empleo

Duration: 12+ months
Job Description:

In this role, you will be responsible for driving low-power design strategies, synthesis, and timing closure for complex SoC and IP designs. You will use industry-standard EDA tools to optimize power, performance, and area (PPA), ensuring efficient, reliable silicon that meets product requirements.

Duration: 12+ months
Job Description:

In this role, you will be responsible for driving low-power design strategies, synthesis, and timing closure for complex SoC and IP designs. You will use industry-standard EDA tools to optimize power, performance, and area (PPA), ensuring efficient, reliable silicon that meets product requirements.

The Person:

You are passionate about digital design, power optimization, and timing closure in advanced semiconductor technologies. You enjoy solving challenging problems, are detail-oriented, and thrive in a collaborative team environment and passionate to work with vibrant team located in different time zone . With strong analytical skills and a methodical approach, you are eager to learn, share knowledge, and contribute to building cutting-edge silicon.

Key Responsibilities:

• Develop and implement power reduction strategies across SoC/IP design.
• Perform synthesis and static timing analysis (STA) to achieve PPA targets.
• Analyze and optimize dynamic and leakage power using industry-standard tools.
• Work closely with RTL designers, physical design, and verification teams to ensure timing and power requirements are met.
• Run low-power verification checks (UPF/CPF) and validate correct power intent implementation.
• Support sign-off activities for Lint , CDC , synthesis, timing, and power closure.
• Automate and streamline power and timing workflows to improve efficiency.
• Build test plan documentation, accounting for interactions with other features, the hardware.

Duration: 12+ months
Job Description:

In this role, you will be responsible for driving low-power design strategies, synthesis, and timing closure for complex SoC and IP designs. You will use industry-standard EDA tools to optimize power, performance, and area (PPA), ensuring efficient, reliable silicon that meets product requirements.

The Person:

You are passionate about digital design, power optimization, and timing closure in advanced semiconductor technologies. You enjoy solving challenging problems, are detail-oriented, and thrive in a collaborative team environment and passionate to work with vibrant team located in different time zone . With strong analytical skills and a methodical approach, you are eager to learn, share knowledge, and contribute to building cutting-edge silicon.

Key Responsibilities:

• Develop and implement power reduction strategies across SoC/IP design.
• Perform synthesis and static timing analysis (STA) to achieve PPA targets.
• Analyze and optimize dynamic and leakage power using industry-standard tools.
• Work closely with RTL designers, physical design, and verification teams to ensure timing and power requirements are met.
• Run low-power verification checks (UPF/CPF) and validate correct power intent implementation.
• Support sign-off activities for Lint , CDC , synthesis, timing, and power closure.
• Automate and streamline power and timing workflows to improve efficiency.
• Build test plan documentation, accounting for interactions with other features, the hardware.

Preferred Experience:

• Strong background in ASIC synthesis and static timing analysis (STA).
• Hands-on expertise with EDA tools such as Synopsys Design Compiler, PrimeTime, PrimePower, Power Artists , or equivalent.
• Experience with power analysis and optimization techniques (clock gating, multi-Vt, power gating, multi-voltage design).
• Familiarity with UPF/CPF power intent specification and verification.
• Solid understanding of digital design fundamentals, RTL coding (Verilog/SystemVerilog).
• Experience with advanced process nodes (e.g., 7nm, 5nm, 3nm) is a strong plus.
• Proficiency in scripting languages (TCL, Perl, Python, or Shell) for flow automation.
• Exposure to floorplanning, place-and-route, and ECO flows is desirable.
• Knowledge of low-power design methodologies and trade-offs.
• Prior leadership, mentorship, or cross-functional collaboration experience is an asset.
• Experienced with Verilog, System Verilog, C, and C++
• Graphics pipeline knowledge
• Automating workflows in a distributed compute environment.

About US Tech Solutions:

US Tech Solutions is a global staff augmentation firm providing a wide range of talent on-demand and total workforce solutions. To know more about US Tech Solutions, please visit www.ustechsolutions.com.

US Tech Solutions is an Equal Opportunity Employer.

All qualified applicants will receive consideration for employment without regard to race, colour, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

AI Statement:

By applying, you acknowledge that AI-assisted tools may be used during hiring.