ASIC Digital Verification, Staff Engineer

Synopsys, Inc.; Ottawa; On-site; CAD 80,000 - 120,000; Full time

Job summary

An established industry player is seeking a talented verification engineer to lead innovative projects in digital verification. This role involves defining verification plans and utilizing advanced techniques to ensure product quality in cutting-edge technology areas such as AI and IoT. You will work closely with cross-functional teams, providing mentorship and driving the verification process from start to finish. If you are passionate about technology and eager to make an impact on new product architectures, this is the opportunity for you. Join a forward-thinking company that values creativity and collaboration, and take your career to the next level.

Qualifications

• 8+ years of digital verification experience in the industry.
• Proficient in HDL languages like System Verilog and Verilog.

Responsibilities

• Define verification plans and build environments for IP level designs.
• Provide technical leadership to junior engineers and interns.

Skills

Digital Verification

System Verilog

UVM

C

C++

Analytical Skills

Communication Skills

Education

Bachelor's Degree

Master's Degree

Tools

Verilog

VHDL

Job description

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities, meet unique performance, power, and size requirements of their target applications, and get differentiated products to market quickly with reduced risk.

Responsibilities

1. Define verification plans and build verification environments for IP level designs using System Verilog with UVM.
2. Apply advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification to achieve functional verification for Serdes applications.
3. Write test cases, checkers, and coverage that implement the verification test plan.
4. Provide technical leadership to junior engineers and interns.

Job Requirements

1. Bachelors or Masters with 8+ years of digital verification experience in the industry.
2. RTL verification using coverage driven verification techniques.
3. Scripting in any language. Programming experience or coursework in C, C++.
4. Proficient in HDL languages System Verilog, Verilog, or VHDL.
5. Good analytical, oral, and written communication skills.
6. Self-motivated, proactive team player.

Unique opportunities presented with this position

1. To grow and manage verification of product end-to-end.
2. Cross-functional learning and interaction with professional teams across domains and geographies.
3. Develop systematic ways to address new problems, think outside of the box.
4. Have an impact on the new product architectures, quality, and development strategies.