ASIC Digital Verification, Staff Engineer

Synopsys Inc; Ottawa; On-site; CAD 80,000 - 120,000; Full time

Job summary

An established industry player seeks a skilled ASIC Digital Verification Engineer to lead verification efforts in cutting-edge technology projects. This role involves defining verification plans, utilizing advanced techniques like constrained random generation, and providing mentorship to junior engineers. Join a forward-thinking company that is at the forefront of innovations such as self-driving cars and AI, and contribute to impactful product architectures and development strategies. If you are passionate about driving technological advancements and thrive in a collaborative environment, this opportunity is perfect for you.

Qualifications

• 8+ years of digital verification experience with a Bachelor's or Master's degree.
• Proficiency in HDL languages like SystemVerilog and Verilog.

Responsibilities

• Define verification plans and build environments for IP-level designs.
• Provide technical leadership to junior engineers and interns.

Skills

Digital Verification

SystemVerilog

UVM

C

C++

Analytical Skills

Communication Skills

Education

Bachelor's Degree

Master's Degree

Tools

Verilog

VHDL

Job description

Join to apply for the ASIC Digital Verification, Staff Engineer role at Synopsys Inc

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars, Artificial Intelligence, the cloud, 5G, and the Internet of Things are ushering in the Era of Smart Everything. We power these breakthroughs with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our Silicon IP business focuses on integrating more capabilities into SoCs—faster. We offer the broadest portfolio of silicon IP—pre-designed blocks of logic, memory, interfaces, analog, security, and embedded processors—to help customers meet performance, power, and size requirements and bring differentiated products to market quickly with reduced risk.

Responsibilities

1. Define verification plans and build verification environments for IP-level designs using SystemVerilog with UVM.
2. Apply advanced verification techniques such as constrained random generation, functional coverage, assertions, and formal verification for Serdes applications.
3. Write test cases, checkers, and coverage to implement the verification test plan.
4. Provide technical leadership to junior engineers and interns.

Job Requirements

1. Bachelor's or Master's degree with 8+ years of digital verification experience.
2. RTL verification experience using coverage-driven verification techniques.
3. Scripting skills in any language; programming experience or coursework in C, C++.
4. Proficiency in HDL languages such as SystemVerilog, Verilog, or VHDL.
5. Good analytical, oral, and written communication skills.
6. Self-motivated, proactive team player.

Unique Opportunities

1. Grow and manage verification of end-to-end product development.
2. Engage in cross-functional learning and collaboration across domains and geographies.
3. Develop systematic approaches to new problems and think innovatively.
4. Impact new product architectures, quality, and development strategies.

Additional Details

• Seniority level: Mid-Senior level
• Employment type: Full-time
• Job function: Design, Consulting, and Engineering
• Industries: Semiconductor Manufacturing, Software Development, and Computer Hardware Manufacturing