Application Specific Integrated Circuit Design Engineer

Raas Infotek; Canada; Remote; CAD 100,000 - 140,000; Full time

Job summary

Raas Infotek is seeking an Application Specific Integrated Circuit Design Engineer to join their team. This role involves designing and implementing advanced display technologies in a collaborative environment, requiring deep technical knowledge and strong problem-solving skills. The ideal candidate will possess a minimum of 10 years' experience in ASIC design and proficiency in Verilog and SystemVerilog. This opportunity offers remote flexibility and the chance to lead projects in a dynamic team setting.

Qualifications

• Minimum 10 years of ASIC design work experience.
• In-depth knowledge of design processes from specification to verification.
• Experience with multi-clock domain designs and IP development.

Responsibilities

• Develop and implement display technologies with design requirements.
• Mentor junior engineers and resolve architectural issues.
• Execute validation plans and testing specifications.

Skills

Verilog

SystemVerilog

Analytical thinking

Problem-solving skills

Teamwork

Interpersonal skills

Tools

Perl

Python

JIRA

GIT

Confluence

Job description

Application Specific Integrated Circuit Design Engineer

Application Specific Integrated Circuit Design Engineer

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Location: Remote

Contract

• The candidate would work closely with a team of designers, architects, and verification engineers to design and implement various display technologies.

KEY RESPONSIBILITIES:

• Develop well designed and qualified display features

• Lead micro-architecture and design efforts based on high level architectural requirements

• Able to build complex systems to meet various design requirements including (but not limited to) functionality, performance, power, area, scalability and testability.

• Timely develop functional and implementation specifications, as well as test plans

• Develop and execute implementation and validation plans of the feature. Proactively driving and resolving any issues that may arise during the development stage

• Resolve pre-layout and post-layout timing and functional eco issues

• Mentor junior engineers to complete their tasks.

PREFERRED EXPERIENCE:

• Minimum 10 years of ASIC design work experience

• Have in depth knowledge of entire design process from design specification, defining architecture, micro-architecture, RTL design and functional verification, synthesis, timing and formal verification

• Proficiency of Verilog or SystemVerilog

• Experience with multi-clock domain designs

• Experience in IP development

• Knowledge in video/display standards a plus.

• Strong in both written and verbal communication

• Strong analytical thinking and problem-solving skills

• Good teamwork and interpersonal skills

ARM GLS Skill set.

• Good DV Skill with major GLS work experience.
• Expertise in testbench updates for GLS
• Expertise in Scripting languages perl or python
• Experience with Make, Yaml & Json file systems.
• Experience with 0 delay simulations and post layout simulations with SDF back annotations (Best/Typical/Worst Case analysis).
• Good understanding of RTL synthesis , Static Timing Analysis & LEC Flows.
• Experience with flow optimizations such as Grey/Black-boxing techniques
• Good at communicating requirements/issues with Implementation, PnR and Design teams.
• Working knowledge of Confluence documentation , version system GIT and Project execution with JIRA.

Ritesh Rawat

Raas infotek corporation

262 Chapman road, Suite 105A, Newark, DE-19702

Phone: [phone] Ext: 142,

Seniority level

• Seniority level

  Director

Employment type

• Employment type

  Contract

Job function

• Job function

  Engineering and Information Technology

• Industries

  IT Services and IT Consulting

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