Analog and Mixed-Signal Modelling Architect (Masters or PhD New Grad)

Ciena Corporation; Ottawa; Sur place; CAD 71 000 - 113 000; Plein temps

Avantages offerts par ce poste

Medical, dental, vision plans

401(K) USA & DCPP Canada

Employee Stock Purchase Program

Paid holidays & vacation

Résumé du poste

Ciena Corporation is seeking an Analog & Mixed-Signal Modelling Architect – New Grad to join the DSP team. You will drive design, modeling, and system-level validation of analog/mixed-signal subsystems for high-speed coherent optical modems.

This role blends C++/SystemC with Python/MATLAB simulations, firmware bring‑up, and lab validation. You will work across analog, digital, DSP, and firmware teams, shaping architectural decisions from concept to silicon bring‑up and product deployment.

Qualifications

• Post-graduate degree in Physics or Engineering with a focus on ASIC hardware, comms, or control systems.
• Experience: internship, co-op, or applied project relevant to the role.
• Understanding of analog/mixed-signal processing in high-speed comms.
• Experience writing C++ and/or SystemC behavioral models for hardware-adjacent systems.

Responsabilités

• Define and review system-level analog and mixed-signal functions for coherent optical modems.
• Develop behavioral models of analog/mixed-signal blocks using C++ and SystemC, with firmware register-map interfaces.
• Model PLLs, clocking, filters, DACs, ADCs, SerDes using C++/SystemC-AMS.
• Build/maintain C++ and Python/MATLAB-based verification flows and wrappers.
• Collaborate with analog, digital, DSP, firmware, and lab teams to align specs and validation plans.
• Support ASIC lab bring-up and correlate silicon and lab data with models and simulations.
• Plan design activities and create guidelines and setup docs in Confluence.

Connaissances

C++

SystemC

Python

MATLAB

SystemC-AMS

Linux

Git

Simulink

Cadence Virtuoso

Xcelium AMS

Formation

Post-graduate degree in Physics or Engineering

Outils

Python

MATLAB

Simulink

Cadence Virtuoso

Cadence AMS Designer

Xcelium AMS

Description du poste

As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being—on and off the job. Connect with a career that matters.

Analog & Mixed-Signal Modelling Architect – New Grad

We are seeking a Analog & Mixed-Signal Modelling Architect – New Grad to join our DSP team. In this role, you will drive the design, modeling, and system-level validation of analog and mixed-signal subsystems for next-generation high-speed coherent optical modems. This position emphasizes behavioral modeling using C++ and SystemC, tightly integrated with Python and MATLAB-based system simulations, firmware bring‑up flows, and lab validation. You will operate at the intersection of analog-/digital-hardware, DSP, firmware, and electro‑optical subsystems - contributing architectural decisions from early concept through silicon bring‑up and product deployment.

How you will make an impact:

• Define and review system-level analog and mixed-signal functions for coherent optical modems.
• Develop behavioral models of analog and mixed-signal blocks using C++ and SystemC, emphasizing firmware register‑map interfaces, control, observability, and execution speed.
• Apply C++/ SystemC-AMS to model continuous‑time and mixed-signal behavior of PLLs, clocking systems, filters, DACs, ADCs, SerDes, and related subsystems.
• Build and maintain C++ and Python/MATLAB-based verification flows, including C++ MEX wrappers for system simulation environments.
• Collaborate with analog, digital, DSP, firmware, and lab teams to align models, specifications, and validation plans.
• Support ASIC lab bring‑up and characterization, correlating silicon and lab data with behavioral models and system simulations.
• Plan design activities and create design guidelines, implementation documentation, and setup guides in Confluence.

The must haves:

• Education: Post-graduate degree in Physics or Engineering with a focus on ASIC hardware, communication systems, and/or control systems.
• Experience: Previous internship, co-op, or applied project experience relevant to the role.
• Understanding of analog and mixed-signal processing in high-speed communication systems.
• Experience writing C++ and/or SystemC behavioral models for hardware-adjacent systems.
• Demonstrated ability to operate at the system-architecture level while remaining grounded in real analog behavior and physical impairments.
• Knowledge of analog impairments, including noise, distortion, non-linearity, bandwidth limitations, jitter, and phase noise, and their impact on modem-level performance.
• Strong intuition for analog-digital partitioning, power-performance trade-offs, and calibration strategies.
• Comfortable working in a Linux-based development environment, using Git and modern collaborative workflows.
• Clear technical communication skills and the ability to work effectively across disciplines.
• Experience with the following tools: C++, SystemC-AMS, Python, MATLAB, Simulink, Cadence Virtuoso, Cadence AMS Designer, Xcelium AMS.

The annual salary range for a Masters New Grad is $70,700 - $112,900. The annual salary range for PhD New Grads is $89,000 - $142,200. Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available. Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission.

In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination. Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

Dig deeper into who we are, what we do, and what you can expect as a member of our team. Meet the people who are shaping the future of communication and explore the culture we’ve built together at CienaLife.