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Cadence Design Systems Inc. in Belo Horizonte, Brazil, is looking for a Software Engineer II: Hardware Verification R&D to join the HSV group. You will contribute to ATPG/DFT and Fault Emulation work, develop features for a HW testbench, and collaborate with global teams on emulation platforms. Strong C++ and OS skills, plus English and Portuguese, are required.
The role offers CLT employment, 40 hours/week, and competitive benefits in a fast-paced tech environment at Cadence.
Cadence Design Systems Inc. is looking for a motivated Software Engineer II: Hardware Verification R&D to work with us in Belo Horizonte, Brazil.
At Cadence, we hire and develop leaders and innovators who want to impact the world of technology. Cadence has been nominated as a Great Place to Work globally and in Brazil and is also a Fortune 100 Best Companies to Work For.
As a Software Engineer II: Hardware Verification R&D , you will be part of ATPG/DFT and Fault Emulation team in the HSV group in Belo Horizonte, Brazil. On the ATPG/DFT side, we develop a compiler for the STIL language, generating a HW testbench. On the Fault Emulation side, we work with Functional Safety solutions for the emulation environment.
The ATPG/DFT and Fault Emulation team works with Palladium, the industry leading Emulation platform based on our proprietary hardware. Working at Cadence is very dynamic, fast-paced, and integrated with other teams all around the world.
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About Cadence Design Systems:
Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. For more information, access http://www.cadence.com