Virtual Platform Architect – SoC & System Simulation

imec; Vlaams-Brabant; Presencial; EUR 70.000 - 110.000; Tempo integral

Resumo da vaga

IMEC's Compute System Architecture (CSA) seeks a Virtual Platform R&D Engineer in Leuven, Belgium. You will develop and maintain virtual platforms for SoC architectures, integrating models across abstraction levels and enabling architectural exploration and validation.

You will map workloads on platforms like QEMU, gem5, RTL, and FPGA, while collaborating with senior staff to define project scope and milestones.

Qualificações

• Master’s or PhD in Electrical/Electronics/Computer Engineering/Science or related domain with hands-on compute system architectures.
• Deep understanding of system-level design, modern compute/memory systems and SoC components.
• Proven expertise with simulation frameworks or virtual platforms (QEMU, gem5, SystemC).
• You can model hardware and are a hands-on engineer with research mindset.

Responsabilidades

• Develop, maintain and stitch virtual platforms for complex SoC architectures.
• Build functional and performance models of compute, memory, interconnect and accelerators.
• Implement interfaces between simulation infra and tooling to improve productivity and fidelity.
• Support workload mapping and bring-up on platforms like QEMU, gem5, RTL, FPGA.
• Model and simulate new architectures to analyze trade-offs and bottlenecks.
• Contribute to project scope, timelines, milestones and deliverables with senior staff.
• Mentor students as needed.

Conhecimentos

C/C++

Python

SystemC

QEMU

gem5

RISC-V

Bash

Scripting

English

Formação

Master's degree or PhD in Electrical/Electronics/Computer Engineering/Science

Ferramentas

QEMU

gem5

SystemC

Descrição da vaga

IMEC's Compute System Architecture (CSA) seeks a Virtual Platform R&D Engineer in Leuven, Belgium. You will develop and maintain virtual platforms for SoC architectures, integrating models across abstraction levels and enabling architectural exploration and validation.

You will map workloads on platforms like QEMU, gem5, RTL, and FPGA, while collaborating with senior staff to define project scope and milestones.