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Vivid Resourcing seeks a Senior FPGA Engineer to lead FPGA development for space applications in our engineering team. You will own RTL/VHDL design, drive architectures and coordinate verification across hardware, embedded software and test teams.
You will work on radiation-tolerant, fault-tolerant designs, balancing performance, reliability and power. A high-reliability aerospace background is highly valued, with mentorship for less experienced engineers and involvement in qualification testing.
We're currently recruiting for a Senior FPGA Engineer to join the engineering team and play a key role in the development of advanced FPGA-based electronics for space applications. You will work on complex, highly reliable digital systems for next-generation spacecraft and space-based technologies, taking a leading technical role in designs where reliability, performance and long-term operation are critical.
You will be involved throughout the FPGA development lifecycle, from requirements analysis and architectural definition through RTL design, implementation, verification, hardware integration and qualification. You will contribute to FPGA architecture and key technical decisions around processing, interfaces, resource utilisation, timing and reliability, working closely with hardware, embedded software, systems, verification and test engineers.
As a senior member of the team, you will take technical ownership of FPGA developments, contribute to design reviews and development methodologies, and provide guidance to less experienced engineers where appropriate. The role combines hands‑on development with architectural responsibility, as well as troubleshooting, system‑level testing and supporting the transition from development into qualification and production.
The projects offer an interesting engineering challenge due to the constraints of the space environment. Depending on the application, you may work with requirements around radiation tolerance, fault detection, redundancy and high reliability, while balancing these against FPGA resources, performance and power consumption.