Senior Digital Verification Engineer – SystemVerilog/UVM

Karlstad University; Heverlee; Sur place; EUR 65 000 - 85 000; Plein temps

Avantages offerts par ce poste

Market appropriate salary

Fringe benefits

Opportunities for professional development

Résumé du poste

Karlstad University is looking for a candidate to contribute to the design of complex systems-on-chip (SoCs) for various applications including communication and AI. The ideal applicant would have a MSc or PhD in electronics engineering and strong verification experience using SystemVerilog/UVM.

This role promotes collaborative efforts in a multicultural environment, emphasizing personal and professional growth through training and development opportunities. A competitive salary along with fringe benefits is offered.

Qualifications

• 5+ years of relevant experience in digital circuit verification.
• Strong experience with digital circuit verification in SystemVerilog/UVM.
• Experience with designing CPU and peripheral (sub-)systems.
• Understanding of the digital ASIC-design flow.

Responsabilités

• Contribute to the design of complex SoCs for various applications.
• Collaborate with teams for debugging and quality improvement.
• Develop high-quality reports and documentation.

Connaissances

SystemVerilog/UVM

TCL and Python

Git

Cadence IC design tools

Low-power designs

FPGA-development

Formation

MSc or PhD in electronics engineering

Description du poste

Karlstad University is looking for a candidate to contribute to the design of complex systems-on-chip (SoCs) for various applications including communication and AI. The ideal applicant would have a MSc or PhD in electronics engineering and strong verification experience using SystemVerilog/UVM.

This role promotes collaborative efforts in a multicultural environment, emphasizing personal and professional growth through training and development opportunities. A competitive salary along with fringe benefits is offered.