CPU Subsystem RTL & Verification Designer (Contract)

Karlstad University; Heverlee; Sur place; EUR 60 000 - 80 000; Plein temps

Avantages offerts par ce poste

Market appropriate salary

Fringe benefits

Opportunities for personal development

Résumé du poste

Karlstad University is seeking a Digital Designer for a temporary assignment in Leuven, Belgium. You will focus on the design and verification of CPU subsystems using RTL design for imec's RISC-V-based compute platforms.

This role involves collaboration with architecture teams, ensuring that high-quality designs feed into innovative prototypes used across various domains. Candidates should have strong expertise in SystemVerilog and functional verification processes.

Qualifications

• At least 5 years of hands-on RTL design experience.
• Solid grasp of CPU microarchitecture.
• Strong functional verification capability.
• Familiarity with standard interconnect protocols.
• Experience with industry EDA flows.
• Comfort with scripting for automation.

Responsabilités

• Translate specifications into synthesizable RTL for CPU blocks.
• Integrate RISC-V cores with subsystem components.
• Develop and execute functional verification environments.
• Collaborate with architects to refine specifications.
• Document design and verification intent clearly.

Connaissances

RTL design

SystemVerilog

Functional verification

Scripting (Python, Tcl)

Collaboration

Outils

EDA tools (Synopsys, Cadence, Siemens)

Description du poste

Karlstad University is seeking a Digital Designer for a temporary assignment in Leuven, Belgium. You will focus on the design and verification of CPU subsystems using RTL design for imec's RISC-V-based compute platforms.

This role involves collaboration with architecture teams, ensuring that high-quality designs feed into innovative prototypes used across various domains. Candidates should have strong expertise in SystemVerilog and functional verification processes.