Senior DFT Architect (remote)

VeroTech; Belgique; Hybride; EUR 90 000 - 130 000; Plein temps

Avantages offerts par ce poste

Company car

Monthly net allowances

Yearly bonus

Insurances

Meal vouchers

Eco-cheques

Résumé du poste

VeroTech is seeking a Sr. DFT Architect to lead the implementation and validation of advanced DFT techniques across complex SoCs.

You will influence test quality, coverage and silicon success, defining test modes and timing constraints, and supporting post-silicon validation. The role requires senior ASIC design experience with DFT insertion and ATPG, leadership, and proficiency in Verilog/VHDL, IEEE testing standards, and modern EDA tools.

Qualifications

• Master’s degree in electronics or electrical engineering.

Responsabilités

• Define DFT architecture and lead its implementation across SoCs and key subsystems.
• Define and manage test modes, timing constraints, and DFT integration.
• Drive implementation of scan-based test, memory test, and on-chip test control structures.
• Generate and debug ATPG patterns to improve fault coverage.
• Collaborate with physical design to resolve timing and routing challenges.
• Support test engineering on (post) silicon validation and debugging.

Connaissances

DFT knowledge

ATPG

Verilog

VHDL

IEEE 1149.1/1149.6/1687

TCL scripting

Python scripting

Shell scripting

Leadership/mentoring

Formation

Master’s degree in electronics or electrical engineering

Outils

Synopsys Fusion Compiler

TestMax

Tessent

Description du poste

Join VeroTech as a Sr. DFT Architect and become part of our community where innovation and people come first. You’ll take on exciting technical challenges and develop your expertise while creating solutions that drive progress across several industries.

About The Role

As a Sr. DFT Engineer, you’ll be at the forefront of implementing and validating advanced DFT techniques on complex SoCs and subsystems. Your work will directly influence test quality, coverage, and silicon success, from defining test modes and timing constraints to supporting post-silicon validation.

Key responsibilities

• Define DFT architecture and lead its implementation across SoCs and key subsystems.
• Define and manage test modes, timing constraints, and DFT integration.
• Drive implementation of scan-based test, memory test, and on-chip test control structures.
• Generate and debug ATPG patterns to improve fault coverage.
• Collaborate with physical design to resolve timing and routing challenges.
• Support test engineering on (post) silicon validation and debugging.

What we're looking for

We are seeking an senior ASIC designer with solid DFT experience. Ideal candidates will have the following:

• Master’s degree in electronics or electrical engineering with 10+ years in digital ASIC design, focusing on DFT insertion and ATPG.
• Recent technical leadership & mentoring experience guiding DFT flows and methodology.
• Proficiency in Verilog or VHDL for test logic development.
• Strong knowledge in IC standards like IEEE 1149.1, 1149.6, and 1687 (IJTAG) for testing & manufacturability.
• Hands-on experience with advanced EDA tools like Synopsys Fusion Compiler + TestMax or Siemens/Mentor Graphics' Tessent.
• Proficiency in TCL and other scripting languages like Python & Shell.
• If you work remotely, you're open to fly in 1 week per month.

At VeroTech, you’re part of a real community where engineers grow and thrive together while working on cutting-edge projects in several sectors, enjoying flexibility and true support from colleagues. We offer personalized career development tailored to your ambitions, hybrid work options, and a strong focus on learning and growth. You’ll enjoy regular teambuilding activities in a collaborative environment, along with a broad salary package that includes a company car, monthly net allowances, a yearly bonus, insurances, meal vouchers and eco-cheques.

More than just shaping technology, at VeroTech we're shaping the future. Are you ready to shape yours?