Senior Analog Chiptop Designer – Image Sensor ICs

Sony Depthsensing Solutions; Brussel Hoofdstad; Sur place; EUR 85 000 - 120 000; Plein temps

Résumé du poste

Sony Depthsensing Solutions in Brussels seeks an experienced Analog Chiptop Design Engineer to drive top‑level sensor designs for next‑generation image sensors. You will collaborate with analog, logic and pixel teams to deliver robust chiptop solutions that enable first silicon success.

Responsibilities include chiptop productization, IO pads and ESD, power and clock distribution, and tight interaction with design, back‑end, device and packaging teams.

Qualifications

• Master’s degree in electrical engineering or equivalent.
• 5+ years in analog/chiptop design with responsibilities as described above.
• Background in analog design engineering with layout at top level of chips with recent nodes.
• Strong communications skills and ability to work with multiple design teams.

Responsabilités

• You will work on productization of sensors: chiptop level design with physical, electrical and optical considerations.
• You will perform full-cycle follow-up from conception to design to verifications.
• You implement the TOP level of the sensor (IO pads, ESD IO body, wafer connectivity) with daily interaction with design teams.
• You are responsible for ESD protection of the sensor and support mask improvement after tape-out.
• You are the interface among the Design environment, the Device and the Design team.

Connaissances

English proficiency

Top-level chiptop design

Layout design at top level

Communication skills

Unix scripting (SKILL/Ocean)

Collaborative teamwork

Travel willingness

Formation

Master’s degree in electrical engineering or equivalent

Outils

Cadence Virtuoso

Assura

Calibre

Synopsys StarRC

Cadence QRC

Description du poste

Sony Depthsensing Solutions in Brussels seeks an experienced Analog Chiptop Design Engineer to drive top‑level sensor designs for next‑generation image sensors. You will collaborate with analog, logic and pixel teams to deliver robust chiptop solutions that enable first silicon success.

Responsibilities include chiptop productization, IO pads and ESD, power and clock distribution, and tight interaction with design, back‑end, device and packaging teams.