Process Optimization and Characterization of Tight Pitch Dielectric Etch for CFET MOL Integration

Imec India Private Limited; Vlaams-Brabant; Sur place; EUR 60 000 - 80 000; Plein temps

Résumé du poste

A research institute in Belgium is seeking a Master's student for an internship and thesis project focused on developing dielectric etching processes for advanced semiconductor technologies. The project will explore challenges in etching processes, evaluate different chemistries, and analyze results using advanced techniques. Interested candidates with a Master's degree in relevant fields such as Chemistry or Physics are encouraged to apply.

Qualifications

• Master's degree in Chemistry, Chemical Engineering, Materials Engineering, Nanoscience, or Physics.
• Ability to develop CFET MOL dielectric etch processes.
• Familiarity with plasma etch chemistries.

Responsabilités

• Develop CFET MOL dielectric etch processes at specific pitches.
• Evaluate plasma etch chemistries for high anisotropy and selectivity.
• Study etch-induced damage and its impact on downstream metallization.

Connaissances

Plasma etch chemistries

SEM/CD-SEM analysis

Understanding etching process challenges

Formation

Master's degree in relevant field

Outils

TEM analysis

Description du poste

Overview

Summary of Research Project:

As the semiconductor industry moves beyond FinFETs toward Complementary FETs (CFETs) to enable continued transistor scaling, the Middle of Line (MOL) interconnect region faces new challenges. CFET requires tight-pitch dielectric etching to integrate vias and contacts in vertically stacked N/P devices. The project aims to investigate and optimize dielectric etch processes for ≤50nm pitch CFET middle-of-line (MOL) integration.

The reliability and performance of CFET devices depend on the etch process quality in these dense regions, especially:

1. Minimizing etch-induced damage to underlying or adjacent features.
2. Maintaining critical dimension (CD) control and profile control.
3. Achieving high anisotropy with low line edge roughness (LER).
4. Etch process selectivity to hardmask and spacer material etc.

The intern will work on:

• CFET MOL dielectric etch process development at pitch 60nm and 50nm – Dep/Etch cyclic etch process vs. QALE (quasi atomic layer etching).
• Understanding and compare etching process challenges for two different pitch – 60nm vs. 50nm (or even smaller, for example 42nm).
• Investigating hardmask and spacer strategies to enable tight pitch fidelity.
• Evaluating plasma etch chemistries (e.g., fluorocarbon-based, H2/N2-based) for high anisotropy and selectivity.
• Evalutaing low temperature (cryo) plasma etch benefit compared to conventional etch process.
• Studying etch-induced damage and its impact on downstream metallization.
• Using SEM/CD-SEM and TEM analysis to assess profile, CD, and etch residue.

Type of Project: Combination of internship and thesis

Master's degree: Master of Science; Master of Engineering Science

Master program:Chemistry/Chemical Engineering; Materials Engineering; Nanoscience & Nanotechnology; Physics

Duration: 1 year

For more information or application, please contact the supervising scientist Tanushree Sarkar ([e-mail]).