ASIC Digital Verification Design, Staff Engineer

Synopsys, Inc.; Mississauga; Sur place; CAD 80 000 - 110 000; Plein temps

Résumé du poste

An innovative firm is seeking a highly motivated individual to join their PHY Digital Design Verification team in Mississauga. This position offers a unique opportunity to engage with cutting-edge technologies, including PCIe, USB, and MIPI SERDES products. The successful candidate will work closely with skilled engineers to ensure the delivery of high-end mixed-signal designs. If you are passionate about digital design and verification, and thrive in a dynamic environment, this role could be your next big step in the tech industry.

Qualifications

• 5+ years of experience in digital design or verification positions.
• Experience in writing test cases in Verilog and SystemVerilog.

Responsabilités

• Define and track Verification Testplans for SERDES products.
• Design and write constrained-random SystemVerilog testbenches.

Connaissances

SystemVerilog

Verilog

Digital Design

Debugging

Python

Communication Skills

Organizational Skills

Formation

BS in Computer Engineering

MS in Computer Engineering

Outils

Jira

Description du poste

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

Seeking a highly motivated individual to join our PHY Digital Design Verification team based in Mississauga, Canada. The candidate will be involved in verifying current and next generation PCIe, USB 3/4, and/or MIPI CPHY/DPHY SERDES products. The position offers an excellent opportunity to work with digital and mixed signal design engineers accountable for delivering high-end mixed-signal designs.

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Responsibilities:

• Defining and tracking Verification Testplans
• Designing and writing constrained-random SystemVerilog testbenches using a Verification Methodology such as UVM (Universal Verification Methodology)
• Creating and examining Functional Coverage
• Writing SystemVerilog assertions
• Debugging RTL and gate-level simulation failures
• Firmware Debug
• Bug Tracking using Software Tools such as Jira
• Code Coverage Analysis

Skills required:

• BS/MS in Computer Engineering or related fields with 5+ years of experience in digital design or verification positions
• Experience in writing testcases in Verilog and System Verilog
• Experience in debugging complex testbench and design related issues
• Solid understanding of digital circuit design
• Familiarity with scripting languages (Python or Perl)
• Self-learner, independent, good organization and communication skills