Senior ASIC Digital Design Engineer – NoC/Interconnect

Meta; Redmond; On-site; AUD 253,000 - 356,000; Full time

Job summary

Meta is seeking highly skilled Design Engineers to join our team in Redmond. You will contribute to the development of advanced technology solutions, including machine learning and network acceleration, designing and optimizing low-power accelerators and SoCs for next-generation devices.

You will collaborate across DV, PD and architecture teams, develop RTL and micro-architecture, and help drive IP and interconnect strategies to meet performance, power, and area targets while embracing

Qualifications

• Bachelor's degree or equivalent in CS/CE or related field.
• 8+ years as a hardware design engineer for production silicon.
• Experience in digital design architecture, RTL coding and micro-architecture development.
• Ability to communicate design decisions to verification, physical design and architecture teams.

Responsibilities

• Contribute to ASIC digital µArchitecture and design.
• Assist performance/power analysis to meet targets.
• Map algorithms onto hardware and specify IP/subsystem integration requirements.
• Collaborate with Verification, Physical Design and Design-for-Test teams.
• Develop micro-architecture, RTL coding and verification for complex IPs.
• Drive IP/sub-system micro-architecture and RTL design with DV and PD leads.

Skills

ASIC design

RTL coding

Micro-architecture

Power/performance analysis

Interconnect/IP integration

DV/PD collaboration

Cross-functional communication

Education

Bachelor's degree in CS/CE or related field

Job description

Meta is seeking highly skilled Design Engineers to join our team in Redmond. You will contribute to the development of advanced technology solutions, including machine learning and network acceleration, designing and optimizing low-power accelerators and SoCs for next-generation devices.

You will collaborate across DV, PD and architecture teams, develop RTL and micro-architecture, and help drive IP and interconnect strategies to meet performance, power, and area targets while embracing